/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2016-2018 Linaro Ltd. */ #ifndef HISI_ISP_CVDR_H #define HISI_ISP_CVDR_H #include #include #include #include #include #include #define ISP_CVDR_PAD_SINK 0 #define ISP_CVDR_PAD_SRC 1 #define ISP_CVDR_PADS_NUM 1 #define CVDR_SRT_CVDR_CFG_REG 0x0 #define CVDR_RT_CVDR_CFG_REG 0x0 #define CVDR_SRT_VP_WR_IF_CFG_0_REG 0x28 #define CVDR_SRT_VP_RD_IF_CFG_0_REG 0x514 #define CVDR_CVDR_CVDR_CFG_REG 0x0 #define CVDR_CVDR_CVDR_DEBUG_EN_REG 0x4 #define CVDR_CVDR_CVDR_DEBUG_REG 0x8 #define CVDR_CVDR_CVDR_WR_QOS_CFG_REG 0xC #define CVDR_CVDR_CVDR_RD_QOS_CFG_REG 0x10 #define CVDR_CVDR_OTHER_RO_REG 0x14 #define CVDR_CVDR_OTHER_RW_REG 0x18 #define CVDR_CVDR_VP_WR_CFG_0_REG 0x1C #define CVDR_CVDR_VP_WR_AXI_FS_0_REG 0x20 #define CVDR_CVDR_VP_WR_AXI_LINE_0_REG 0x24 #define CVDR_CVDR_VP_WR_IF_CFG_0_REG 0x28 #define CVDR_CVDR_VP_WR_CFG_1_REG 0x2C #define CVDR_CVDR_VP_WR_AXI_FS_1_REG 0x30 #define CVDR_CVDR_VP_WR_AXI_LINE_1_REG 0x34 #define CVDR_CVDR_VP_WR_IF_CFG_1_REG 0x38 #define CVDR_CVDR_VP_WR_CFG_2_REG 0x3C #define CVDR_CVDR_VP_WR_AXI_FS_2_REG 0x40 #define CVDR_CVDR_VP_WR_AXI_LINE_2_REG 0x44 #define CVDR_CVDR_VP_WR_IF_CFG_2_REG 0x48 #define CVDR_CVDR_VP_WR_CFG_3_REG 0x4C #define CVDR_CVDR_VP_WR_AXI_FS_3_REG 0x50 #define CVDR_CVDR_VP_WR_AXI_LINE_3_REG 0x54 #define CVDR_CVDR_VP_WR_IF_CFG_3_REG 0x58 #define CVDR_CVDR_VP_WR_CFG_4_REG 0x5C #define CVDR_CVDR_VP_WR_AXI_FS_4_REG 0x60 #define CVDR_CVDR_VP_WR_AXI_LINE_4_REG 0x64 #define CVDR_CVDR_VP_WR_IF_CFG_4_REG 0x68 #define CVDR_CVDR_VP_WR_CFG_5_REG 0x6C #define CVDR_CVDR_VP_WR_AXI_FS_5_REG 0x70 #define CVDR_CVDR_VP_WR_AXI_LINE_5_REG 0x74 #define CVDR_CVDR_VP_WR_IF_CFG_5_REG 0x78 #define CVDR_CVDR_VP_WR_CFG_8_REG 0x9C #define CVDR_CVDR_VP_WR_AXI_FS_8_REG 0xA0 #define CVDR_CVDR_VP_WR_AXI_LINE_8_REG 0xA4 #define CVDR_CVDR_VP_WR_IF_CFG_8_REG 0xA8 #define CVDR_CVDR_VP_WR_CFG_9_REG 0xAC #define CVDR_CVDR_VP_WR_AXI_FS_9_REG 0xB0 #define CVDR_CVDR_VP_WR_AXI_LINE_9_REG 0xB4 #define CVDR_CVDR_VP_WR_IF_CFG_9_REG 0xB8 #define CVDR_CVDR_VP_WR_CFG_10_REG 0xBC #define CVDR_CVDR_VP_WR_AXI_FS_10_REG 0xC0 #define CVDR_CVDR_VP_WR_AXI_LINE_10_REG 0xC4 #define CVDR_CVDR_VP_WR_IF_CFG_10_REG 0xC8 #define CVDR_CVDR_VP_WR_CFG_11_REG 0xCC #define CVDR_CVDR_VP_WR_AXI_FS_11_REG 0xD0 #define CVDR_CVDR_VP_WR_AXI_LINE_11_REG 0xD4 #define CVDR_CVDR_VP_WR_IF_CFG_11_REG 0xD8 #define CVDR_CVDR_VP_WR_CFG_12_REG 0xDC #define CVDR_CVDR_VP_WR_AXI_FS_12_REG 0xE0 #define CVDR_CVDR_VP_WR_AXI_LINE_12_REG 0xE4 #define CVDR_CVDR_VP_WR_IF_CFG_12_REG 0xE8 #define CVDR_CVDR_VP_WR_CFG_14_REG 0xFC #define CVDR_CVDR_VP_WR_AXI_FS_14_REG 0x100 #define CVDR_CVDR_VP_WR_AXI_LINE_14_REG 0x104 #define CVDR_CVDR_VP_WR_IF_CFG_14_REG 0x108 #define CVDR_CVDR_VP_WR_CFG_15_REG 0x10C #define CVDR_CVDR_VP_WR_AXI_FS_15_REG 0x110 #define CVDR_CVDR_VP_WR_AXI_LINE_15_REG 0x114 #define CVDR_CVDR_VP_WR_IF_CFG_15_REG 0x118 #define CVDR_CVDR_VP_WR_CFG_16_REG 0x11C #define CVDR_CVDR_VP_WR_AXI_FS_16_REG 0x120 #define CVDR_CVDR_VP_WR_AXI_LINE_16_REG 0x124 #define CVDR_CVDR_VP_WR_IF_CFG_16_REG 0x128 #define CVDR_CVDR_VP_WR_CFG_17_REG 0x12C #define CVDR_CVDR_VP_WR_AXI_FS_17_REG 0x130 #define CVDR_CVDR_VP_WR_AXI_LINE_17_REG 0x134 #define CVDR_CVDR_VP_WR_IF_CFG_17_REG 0x138 #define CVDR_CVDR_VP_WR_CFG_18_REG 0x13C #define CVDR_CVDR_VP_WR_AXI_FS_18_REG 0x140 #define CVDR_CVDR_VP_WR_AXI_LINE_18_REG 0x144 #define CVDR_CVDR_VP_WR_IF_CFG_18_REG 0x148 #define CVDR_CVDR_VP_WR_CFG_19_REG 0x14C #define CVDR_CVDR_VP_WR_AXI_FS_19_REG 0x150 #define CVDR_CVDR_VP_WR_AXI_LINE_19_REG 0x154 #define CVDR_CVDR_VP_WR_IF_CFG_19_REG 0x158 #define CVDR_CVDR_VP_WR_CFG_20_REG 0x15C #define CVDR_CVDR_VP_WR_AXI_FS_20_REG 0x160 #define CVDR_CVDR_VP_WR_AXI_LINE_20_REG 0x164 #define CVDR_CVDR_VP_WR_IF_CFG_20_REG 0x168 #define CVDR_CVDR_VP_WR_CFG_21_REG 0x16C #define CVDR_CVDR_VP_WR_AXI_FS_21_REG 0x170 #define CVDR_CVDR_VP_WR_AXI_LINE_21_REG 0x174 #define CVDR_CVDR_VP_WR_IF_CFG_21_REG 0x178 #define CVDR_CVDR_VP_WR_CFG_22_REG 0x17C #define CVDR_CVDR_VP_WR_AXI_FS_22_REG 0x180 #define CVDR_CVDR_VP_WR_AXI_LINE_22_REG 0x184 #define CVDR_CVDR_VP_WR_IF_CFG_22_REG 0x188 #define CVDR_CVDR_VP_WR_CFG_23_REG 0x18C #define CVDR_CVDR_VP_WR_AXI_FS_23_REG 0x190 #define CVDR_CVDR_VP_WR_AXI_LINE_23_REG 0x194 #define CVDR_CVDR_VP_WR_IF_CFG_23_REG 0x198 #define CVDR_CVDR_VP_WR_CFG_24_REG 0x19C #define CVDR_CVDR_VP_WR_AXI_FS_24_REG 0x1A0 #define CVDR_CVDR_VP_WR_AXI_LINE_24_REG 0x1A4 #define CVDR_CVDR_VP_WR_IF_CFG_24_REG 0x1A8 #define CVDR_CVDR_VP_WR_CFG_25_REG 0x1AC #define CVDR_CVDR_VP_WR_AXI_FS_25_REG 0x1B0 #define CVDR_CVDR_VP_WR_AXI_LINE_25_REG 0x1B4 #define CVDR_CVDR_VP_WR_IF_CFG_25_REG 0x1B8 #define CVDR_CVDR_VP_WR_CFG_26_REG 0x1BC #define CVDR_CVDR_VP_WR_AXI_FS_26_REG 0x1C0 #define CVDR_CVDR_VP_WR_AXI_LINE_26_REG 0x1C4 #define CVDR_CVDR_VP_WR_IF_CFG_26_REG 0x1C8 #define CVDR_CVDR_VP_WR_CFG_27_REG 0x1CC #define CVDR_CVDR_VP_WR_AXI_FS_27_REG 0x1D0 #define CVDR_CVDR_VP_WR_AXI_LINE_27_REG 0x1D4 #define CVDR_CVDR_VP_WR_IF_CFG_27_REG 0x1D8 #define CVDR_CVDR_VP_WR_CFG_28_REG 0x1DC #define CVDR_CVDR_VP_WR_AXI_FS_28_REG 0x1E0 #define CVDR_CVDR_VP_WR_AXI_LINE_28_REG 0x1E4 #define CVDR_CVDR_VP_WR_IF_CFG_28_REG 0x1E8 #define CVDR_CVDR_VP_WR_CFG_29_REG 0x1EC #define CVDR_CVDR_VP_WR_AXI_FS_29_REG 0x1F0 #define CVDR_CVDR_VP_WR_AXI_LINE_29_REG 0x1F4 #define CVDR_CVDR_VP_WR_IF_CFG_29_REG 0x1F8 #define CVDR_CVDR_VP_WR_CFG_30_REG 0x1FC #define CVDR_CVDR_VP_WR_AXI_FS_30_REG 0x200 #define CVDR_CVDR_VP_WR_AXI_LINE_30_REG 0x204 #define CVDR_CVDR_VP_WR_IF_CFG_30_REG 0x208 #define CVDR_CVDR_VP_WR_CFG_31_REG 0x20C #define CVDR_CVDR_VP_WR_AXI_FS_31_REG 0x210 #define CVDR_CVDR_VP_WR_AXI_LINE_31_REG 0x214 #define CVDR_CVDR_VP_WR_IF_CFG_31_REG 0x218 #define CVDR_CVDR_VP_WR_CFG_32_REG 0x21C #define CVDR_CVDR_VP_WR_AXI_FS_32_REG 0x220 #define CVDR_CVDR_VP_WR_AXI_LINE_32_REG 0x224 #define CVDR_CVDR_VP_WR_IF_CFG_32_REG 0x228 #define CVDR_CVDR_VP_WR_CFG_33_REG 0x22C #define CVDR_CVDR_VP_WR_AXI_FS_33_REG 0x230 #define CVDR_CVDR_VP_WR_AXI_LINE_33_REG 0x234 #define CVDR_CVDR_VP_WR_IF_CFG_33_REG 0x238 #define CVDR_CVDR_VP_WR_CFG_34_REG 0x23C #define CVDR_CVDR_VP_WR_AXI_FS_34_REG 0x240 #define CVDR_CVDR_VP_WR_AXI_LINE_34_REG 0x244 #define CVDR_CVDR_VP_WR_IF_CFG_34_REG 0x248 #define CVDR_CVDR_VP_WR_CFG_35_REG 0x24C #define CVDR_CVDR_VP_WR_AXI_FS_35_REG 0x250 #define CVDR_CVDR_VP_WR_AXI_LINE_35_REG 0x254 #define CVDR_CVDR_VP_WR_IF_CFG_35_REG 0x258 #define CVDR_CVDR_VP_WR_CFG_36_REG 0x25C #define CVDR_CVDR_VP_WR_AXI_FS_36_REG 0x260 #define CVDR_CVDR_VP_WR_AXI_LINE_36_REG 0x264 #define CVDR_CVDR_VP_WR_IF_CFG_36_REG 0x268 #define CVDR_CVDR_VP_WR_CFG_37_REG 0x26C #define CVDR_CVDR_VP_WR_AXI_FS_37_REG 0x270 #define CVDR_CVDR_VP_WR_AXI_LINE_37_REG 0x274 #define CVDR_CVDR_VP_WR_IF_CFG_37_REG 0x278 #define CVDR_CVDR_LIMITER_VP_WR_0_REG 0x400 #define CVDR_VP_RD_NBR (22) #define CVDR_VP_WR_NBR (38) #define CVDR_NR_WR_NBR (4) #define CVDR_NR_RD_NBR (8) #define ONE_REG_OFFSET (0x4) #define VP_WR_REG_OFFSET (0x10) #define ISP_CLK (480) #define DERATE (1.2) #define CVDR_ALIGN_BYTES (16) enum cvdr_pix_fmt_e { DF_1PF8 = 0x0, DF_1PF10 = 0x1, DF_1PF12 = 0x2, DF_1PF14 = 0x3, DF_2PF8 = 0x4, DF_2PF10 = 0x5, DF_2PF12 = 0x6, DF_2PF14 = 0x7, DF_3PF8 = 0x8, DF_3PF10 = 0x9, DF_3PF12 = 0xA, DF_3PF14 = 0xB, DF_D32 = 0xC, DF_D48 = 0xD, DF_D64 = 0xE, DF_FMT_INVALID, }; enum vp_wr_id_e { W12_1 = 0, W12_2 = 1, W6_1 = 2, W6_2 = 3, W5_1_1 = 4, W5_1_2 = 5, W4_1_1 = 8, W4_1_2 = 9, W4_2_1 = 10, W4_2_2 = 11, W7_1 = 12, W13_1 = 14, W13_2 = 15, W1_1 = 16, W1_2 = 17, W14_1 = 18, W14_2 = 19, W11_1 = 20, W11_2 = 21, W2_3 = 22, W2_4 = 23, W2_5 = 24, W8_1 = 25, W3_1 = 26, W2_2 = 27, W2_1 = 28, W15_1 = 29, W16_1 = 30, W16_2 = 31, W17_1 = 32, W17_2 = 33, W19_1 = 34, W19_2 = 35, W20_1 = 36, W20_2 = 37, }; struct cvdr_wr_fmt_desc_t { unsigned int fs_addr; unsigned int last_page; enum cvdr_pix_fmt_e pix_fmt; unsigned char pix_expan; unsigned short line_stride; unsigned short line_wrap; }; struct cvdr_bw_cfg_t { unsigned char bw_limiter0; unsigned char bw_limiter1; unsigned char bw_limiter2; unsigned char bw_limiter3; unsigned char bw_limiter_reload; }; struct cvdr_smmu_cfg_t { unsigned char to_use; unsigned int num; unsigned int smr_nscfg; }; struct cvdr_vp_wr_cfg_t { unsigned char to_use; unsigned char id; struct cvdr_wr_fmt_desc_t fmt; struct cvdr_bw_cfg_t bw; }; struct cvdr_rd_fmt_desc_t { unsigned int fs_addr; unsigned int last_page; enum cvdr_pix_fmt_e pix_fmt; unsigned char pix_expan; unsigned short allocated_du; unsigned short line_size; unsigned short hblank; unsigned short frame_size; unsigned short vblank; unsigned short line_stride; unsigned short line_wrap; }; struct cvdr_vp_rd_cfg_t { unsigned char to_use; unsigned char id; struct cvdr_rd_fmt_desc_t fmt; struct cvdr_bw_cfg_t bw; }; struct cvdr_nr_wr_cfg_t { unsigned char to_use; unsigned char nr_wr_stop_en_du_thr; unsigned char nr_wr_stop_en_flux_ctrl; unsigned char nr_wr_stop_en_pressure; unsigned char nr_wr_stop_ok; unsigned char nr_wr_stop; unsigned char en; struct cvdr_bw_cfg_t bw; }; struct cvdr_nr_rd_cfg_t { unsigned char to_use; unsigned short allocated_du; unsigned char nr_rd_stop_en_du_thr; unsigned char nr_rd_stop_en_flux_ctrl; unsigned char nr_rd_stop_en_pressure; unsigned char nr_rd_stop_ok; unsigned char nr_rd_stop; unsigned char en; struct cvdr_bw_cfg_t bw; }; struct cfg_tab_cvdr_t { struct cvdr_smmu_cfg_t smmu_nr_rd_cfg[CVDR_NR_RD_NBR]; struct cvdr_smmu_cfg_t smmu_vp_wr_cfg[CVDR_VP_WR_NBR]; struct cvdr_smmu_cfg_t smmu_vp_rd_cfg[CVDR_VP_RD_NBR]; struct cvdr_vp_wr_cfg_t vp_wr_cfg[CVDR_VP_WR_NBR]; struct cvdr_vp_rd_cfg_t vp_rd_cfg[CVDR_VP_RD_NBR]; struct cvdr_nr_wr_cfg_t nr_wr_cfg[CVDR_NR_WR_NBR]; struct cvdr_nr_rd_cfg_t nr_rd_cfg[CVDR_NR_RD_NBR]; }; struct cvdr_opt_bw_t { unsigned int srt; unsigned int pclk; unsigned int throughput; }; enum cvdr_dev_e { CVDR_RT = 0, CVDR_SRT = 1, }; enum vp_rd_id_e { R3_1 = 0, R11_1 = 4, R12_1 = 5, R11_2 = 6, R12_2 = 7, R10_1 = 8, R10_2 = 9, R2_1 = 10, R8_1_1 = 11, R8_2_1 = 12, R8_1_2 = 13, R8_2_2 = 14, R13_1 = 15, R13_2 = 16, R5_1_4 = 19, R5_1_5 = 20, R5_1_6 = 21, }; /* Define the union U_CVDR_CFG */ union U_CVDR_CFG { /* Define the struct bits */ struct { unsigned int axiwrite_du_threshold : 6; /* [5..0] */ unsigned int reserved_0 : 2; /* [7..6] */ unsigned int du_threshold_reached : 8; /* [15..8] */ unsigned int max_axiread_id : 5; /* [20..16] */ unsigned int reserved_1 : 3; /* [23..21] */ unsigned int max_axiwrite_id : 5; /* [28..24] */ unsigned int reserved_2 : 1; /* [29] */ unsigned int force_rd_clk_on : 1; /* [30] */ unsigned int force_wr_clk_on : 1; /* [31] */ } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_CVDR_DEBUG_EN */ union U_CVDR_DEBUG_EN { /* Define the struct bits */ struct { unsigned int wr_peak_en : 1; unsigned int reserved_0 : 7; unsigned int rd_peak_en : 1; unsigned int reserved_1 : 23; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_CVDR_DEBUG */ union U_CVDR_DEBUG { /* Define the struct bits */ struct { unsigned int wr_peak : 8; unsigned int rd_peak : 8; unsigned int reserved_0 : 16; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_CVDR_WR_QOS_CFG */ union U_CVDR_WR_QOS_CFG { /* Define the struct bits */ struct { unsigned int wr_qos_threshold_01_stop : 4; unsigned int wr_qos_threshold_01_start : 4; unsigned int wr_qos_threshold_10_stop : 4; unsigned int wr_qos_threshold_10_start : 4; unsigned int wr_qos_threshold_11_stop : 4; unsigned int wr_qos_threshold_11_start : 4; unsigned int reserved_0 : 2; unsigned int wr_qos_min : 2; unsigned int wr_qos_max : 2; unsigned int wr_qos_sr : 2; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_CVDR_RD_QOS_CFG */ union U_CVDR_RD_QOS_CFG { /* Define the struct bits */ struct { unsigned int rd_qos_threshold_01_stop : 4; unsigned int rd_qos_threshold_01_start : 4; unsigned int rd_qos_threshold_10_stop : 4; unsigned int rd_qos_threshold_10_start : 4; unsigned int rd_qos_threshold_11_stop : 4; unsigned int rd_qos_threshold_11_start : 4; unsigned int reserved_0 : 2; unsigned int rd_qos_min : 2; unsigned int rd_qos_max : 2; unsigned int rd_qos_sr : 2; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_OTHER_RO */ union U_CVDR_OTHER_RO { /* Define the struct bits */ struct { unsigned int other_ro : 32; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_OTHER_RW */ union U_CVDR_OTHER_RW { /* Define the struct bits */ struct { unsigned int other_rw : 32; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_VP_WR_CFG */ union U_VP_WR_CFG { /* Define the struct bits */ struct { unsigned int vpwr_pixel_format : 4; unsigned int vpwr_pixel_expansion : 1; unsigned int reserved_0 : 10; unsigned int vpwr_last_page : 17; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_VP_WR_AXI_FS */ union U_VP_WR_AXI_FS { /* Define the struct bits */ struct { unsigned int reserved_0 : 4; unsigned int vpwr_address_frame_start : 28; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_VP_WR_AXI_LINE */ union U_VP_WR_AXI_LINE { /* Define the struct bits */ struct { unsigned int vpwr_line_stride : 10; unsigned int reserved_0 : 5; unsigned int vpwr_line_wrap : 14; unsigned int reserved_1 : 3; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_CVDR_RT_VP_WR_IF_CFG */ union U_VP_WR_IF_CFG { /* Define the struct bits */ struct { unsigned int reserved_0 : 16; unsigned int vp_wr_stop_enable_du_threshold_reached : 1; unsigned int vp_wr_stop_enable_flux_ctrl : 1; unsigned int vp_wr_stop_enable_pressure : 1; unsigned int reserved_1 : 5; unsigned int vp_wr_stop_ok : 1; unsigned int vp_wr_stop : 1; unsigned int reserved_2 : 5; unsigned int vpwr_prefetch_bypass : 1; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_LIMITER_VP_WR */ union U_LIMITER_VP_WR { /* Define the struct bits */ struct { unsigned int vpwr_access_limiter_0 : 4; unsigned int vpwr_access_limiter_1 : 4; unsigned int vpwr_access_limiter_2 : 4; unsigned int vpwr_access_limiter_3 : 4; unsigned int reserved_0 : 8; unsigned int vpwr_access_limiter_reload : 4; unsigned int reserved_1 : 4; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_VP_RD_CFG */ union U_VP_RD_CFG { /* Define the struct bits */ struct { unsigned int vprd_pixel_format : 4; unsigned int vprd_pixel_expansion : 1; unsigned int vprd_allocated_du : 5; unsigned int reserved_0 : 5; unsigned int vprd_last_page : 17; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_VP_RD_LWG */ union U_VP_RD_LWG { /* Define the struct bits */ struct { unsigned int vprd_line_size : 13; unsigned int reserved_0 : 3; unsigned int vprd_horizontal_blanking : 8; unsigned int reserved_1 : 8; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_VP_RD_FHG */ union U_VP_RD_FHG { /* Define the struct bits */ struct { unsigned int vprd_frame_size : 13; unsigned int reserved_0 : 3; unsigned int vprd_vertical_blanking : 8; unsigned int reserved_1 : 8; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_VP_RD_AXI_FS */ union U_VP_RD_AXI_FS { /* Define the struct bits */ struct { unsigned int reserved_0 : 4; unsigned int vprd_axi_frame_start : 28; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_VP_RD_AXI_LINE */ union U_VP_RD_AXI_LINE { /* Define the struct bits */ struct { unsigned int vprd_line_stride : 10; unsigned int reserved_0 : 6; unsigned int vprd_line_wrap : 13; unsigned int reserved_1 : 3; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_VP_RD_IF_CFG */ union U_VP_RD_IF_CFG { /* Define the struct bits */ struct { unsigned int reserved_0 : 16; unsigned int vp_rd_stop_enable_du_threshold_reached : 1; unsigned int vp_rd_stop_enable_flux_ctrl : 1; unsigned int vp_rd_stop_enable_pressure : 1; unsigned int reserved_1 : 5; unsigned int vp_rd_stop_ok : 1; unsigned int vp_rd_stop : 1; unsigned int reserved_2 : 5; unsigned int vprd_prefetch_bypass : 1; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_VP_RD_DEBUG */ union U_VP_RD_DEBUG { /* Define the struct bits */ struct { unsigned int vp_rd_debug : 32; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_LIMITER_VP_RD */ union U_LIMITER_VP_RD { /* Define the struct bits */ struct { unsigned int vprd_access_limiter_0 : 4; unsigned int vprd_access_limiter_1 : 4; unsigned int vprd_access_limiter_2 : 4; unsigned int vprd_access_limiter_3 : 4; unsigned int reserved_0 : 8; unsigned int vprd_access_limiter_reload : 4; unsigned int reserved_1 : 4; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_NR_WR_CFG */ union U_NR_WR_CFG { /* Define the struct bits */ struct { unsigned int reserved_0 : 16; unsigned int nr_wr_stop_enable_du_threshold_reached : 1; unsigned int nr_wr_stop_enable_flux_ctrl : 1; unsigned int nr_wr_stop_enable_pressure : 1; unsigned int reserved_1 : 5; unsigned int nr_wr_stop_ok : 1; unsigned int nr_wr_stop : 1; unsigned int reserved_2 : 5; unsigned int nrwr_enable : 1; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_NR_WR_DEBUG */ union U_NR_WR_DEBUG { /* Define the struct bits */ struct { unsigned int nr_wr_debug : 32; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_LIMITER_NR_WR */ union U_LIMITER_NR_WR { /* Define the struct bits */ struct { unsigned int nrwr_access_limiter_0 : 4; unsigned int nrwr_access_limiter_1 : 4; unsigned int nrwr_access_limiter_2 : 4; unsigned int nrwr_access_limiter_3 : 4; unsigned int reserved_0 : 8; unsigned int nrwr_access_limiter_reload : 4; unsigned int reserved_1 : 4; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_NR_RD_CFG */ union U_NR_RD_CFG { /* Define the struct bits */ struct { unsigned int reserved_0 : 5; unsigned int nrrd_allocated_du : 5; unsigned int reserved_1 : 6; unsigned int nr_rd_stop_enable_du_threshold_reached : 1; unsigned int nr_rd_stop_enable_flux_ctrl : 1; unsigned int nr_rd_stop_enable_pressure : 1; unsigned int reserved_2 : 5; unsigned int nr_rd_stop_ok : 1; unsigned int nr_rd_stop : 1; unsigned int reserved_3 : 5; unsigned int nrrd_enable : 1; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_NR_RD_DEBUG */ union U_NR_RD_DEBUG { /* Define the struct bits */ struct { unsigned int nr_rd_debug : 32; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_LIMITER_NR_RD */ union U_LIMITER_NR_RD { /* Define the struct bits */ struct { unsigned int nrrd_access_limiter_0 : 4; unsigned int nrrd_access_limiter_1 : 4; unsigned int nrrd_access_limiter_2 : 4; unsigned int nrrd_access_limiter_3 : 4; unsigned int reserved_0 : 8; unsigned int nrrd_access_limiter_reload : 4; unsigned int reserved_1 : 4; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_DEBUG */ union U_DEBUG { /* Define the struct bits */ struct { unsigned int debug : 32 ; /* [31..0] */ } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_AXI_CFG_NR_WR */ union U_AXI_CFG_NR_WR { /* Define the struct bits */ struct { unsigned int nr_wr_mid : 6; unsigned int reserved_0 : 26; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_AXI_CFG_NR_RD */ union U_AXI_CFG_NR_RD { /* Define the struct bits */ struct { unsigned int nr_rd_mid : 6; unsigned int reserved_0 : 26; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_AXI_CFG_VP_WR */ union U_AXI_CFG_VP_WR { /* Define the struct bits */ struct { unsigned int vp_wr_mid : 6; unsigned int reserved_0 : 26; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_AXI_CFG_VP_RD */ union U_AXI_CFG_VP_RD { /* Define the struct bits */ struct { unsigned int vp_rd_mid : 6; unsigned int reserved_0 : 26; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_SPARE */ union U_SPARE { /* Define the struct bits */ struct { unsigned int spare : 32; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_VP_WR_SMOOTHING */ union U_VP_WR_SMOOTHING { /* Define the struct bits */ struct { unsigned int vpwr_smoothing_access_limiter_0 : 4; unsigned int vpwr_smoothing_access_limiter_1 : 4; unsigned int vpwr_smoothing_access_limiter_2 : 4; unsigned int vpwr_smoothing_access_limiter_3 : 4; unsigned int vpwr_smoothing_threshold : 7; unsigned int reserved_0 : 9; } bits; /* Define an unsigned member */ unsigned int u32; }; /* Define the union U_VP_WR_DEBUG */ union U_VP_WR_DEBUG { /* Define the struct bits */ struct { unsigned int vp_wr_debug : 32; } bits; /* Define an unsigned member */ unsigned int u32; }; struct S_VP_WR { union U_VP_WR_CFG VP_WR_CFG; union U_VP_WR_AXI_FS VP_WR_AXI_FS; union U_VP_WR_AXI_LINE VP_WR_AXI_LINE; union U_VP_WR_IF_CFG VP_WR_IF_CFG; }; struct S_VP_RD { union U_VP_RD_CFG VP_RD_CFG; union U_VP_RD_LWG VP_RD_LWG; union U_VP_RD_FHG VP_RD_FHG; union U_VP_RD_AXI_FS VP_RD_AXI_FS; union U_VP_RD_AXI_LINE VP_RD_AXI_LINE; union U_VP_RD_IF_CFG VP_RD_IF_CFG; unsigned int VP_RD_DEBUG; }; struct S_NR_WR { union U_NR_WR_CFG NR_WR_CFG; union U_NR_WR_DEBUG NR_WR_DEBUG; union U_LIMITER_NR_WR LIMITER_NR_WR; unsigned int reserved_0; }; struct S_NR_RD { union U_NR_RD_CFG NR_RD_CFG; union U_NR_RD_DEBUG NR_RD_DEBUG; union U_LIMITER_NR_RD LIMITER_NR_RD; unsigned int reserved_0; }; /* Define the global struct */ struct S_CVDR_REGS_TYPE { union U_CVDR_CFG CVDR_CFG ; /* 0x0 */ union U_CVDR_DEBUG_EN CVDR_DEBUG_EN ; /* 0x4 */ union U_CVDR_DEBUG CVDR_DEBUG ; /* 0x8 */ union U_CVDR_WR_QOS_CFG CVDR_WR_QOS_CFG ; /* 0xc */ union U_CVDR_RD_QOS_CFG CVDR_RD_QOS_CFG ; /* 0x10 */ union U_CVDR_OTHER_RO CVDR_OTHER_RO ; /* 0x14 */ union U_CVDR_OTHER_RW CVDR_OTHER_RW ; /* 0x18 */ struct S_VP_WR VP_WR[38] ; /* 0x1c~0x278 */ unsigned int reserved_0[73] ; /* 0x27c~0x39c */ union U_LIMITER_VP_WR LIMITER_VP_WR[38] ; /* 0x400~0x494 */ unsigned int reserved_1[2] ; /* 0x498~0x49c */ struct S_VP_RD VP_RD[22] ; /* 0x500~0x7bc */ unsigned int reserved_2[48] ; /* 0x7c0~0x87c */ union U_LIMITER_VP_RD LIMITER_VP_RD[22] ; /* 0x880~0x8d4 */ unsigned int reserved_3[10] ; /* 0x8d8~0x8fc */ struct S_NR_WR NR_WR[4] ; /* 0x900~0x93c */ unsigned int reserved_4[48] ; /* 0x940~0x9fc */ struct S_NR_RD NR_RD[8] ; /* 0xa00~0xa7c */ unsigned int reserved_5[32] ; /* 0xa80~0xafc */ union U_DEBUG DEBUG[16] ; /* 0xb00~0xb3c */ unsigned int reserved_6[48] ; /* 0xb40~0xbfc */ union U_AXI_CFG_NR_WR AXI_CFG_NR_WR[4] ; /* 0xc00~0xc0c */ unsigned int reserved_7[12] ; /* 0xc10~0xc3c */ union U_AXI_CFG_NR_RD AXI_CFG_NR_RD[8] ; /* 0xc40~0xc5c */ unsigned int reserved_8[8] ; /* 0xc60~0xc7c */ union U_AXI_CFG_VP_WR AXI_CFG_VP_WR[38] ; /* 0xc80~0xd14 */ unsigned int reserved_9[26] ; /* 0xd18~0xd7c */ union U_AXI_CFG_VP_RD AXI_CFG_VP_RD[22] ; /* 0xd80~0xdd4 */ unsigned int reserved_10[10] ; /* 0xdd8~0xdfc */ union U_SPARE SPARE[4] ; /* 0xe00~0xe0c */ union U_VP_WR_SMOOTHING VP_WR_SMOOTHING[20] ; /* 0xe10~0xe5c */ unsigned int reserved_11[40] ; /* 0xe60~0xefc */ union U_VP_WR_DEBUG VP_WR_DEBUG[38] ; /* 0xf00~0xf94 */ }; struct cvdr_device { struct isp *isp; struct v4l2_subdev subdev; struct media_pad pads[ISP_CVDR_PADS_NUM]; void __iomem *cvdr_rt; void __iomem *cvdr_srt; void __iomem *sub_ctrl; unsigned int irq_vic1; }; int isp_cvdr_subdev_init(struct isp *isp, struct cvdr_device *cvdr, const struct resources *res); int isp_cvdr_register_entity(struct cvdr_device *cvdr, struct v4l2_device *v4l2_dev); void isp_cvdr_unregister_entity(struct cvdr_device *cvdr); #endif /* HISI_ISP_CVDR_H */