diff options
Diffstat (limited to 'arch/arm64/boot/dts/actions/s900.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/actions/s900.dtsi | 48 |
1 files changed, 47 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index eb35cf78ab73..4dbc5717934c 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/actions,s900-cmu.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/owl-s900-powergate.h> #include <dt-bindings/reset/actions,s900-reset.h> / { @@ -176,7 +177,7 @@ }; sps: power-controller@e012e000 { - compatible = "actions,s900-sps"; + compatible = "actions,s900-sps", "simple-pm-bus"; reg = <0x0 0xe012e000 0x0 0x2000>; #power-domain-cells = <1>; }; @@ -329,5 +330,50 @@ dma-names = "mmc"; status = "disabled"; }; + + usbdrd3_0: usb@e0400000 { + compatible = "actions,s900-dwc3"; + reg = <0x0 0xe040cd00 0x0 0x0c>; + clocks = <&cmu CLK_USB3_480MPLL0>, + <&cmu CLK_USB3_480MPHY0>, + <&cmu CLK_USB3_5GPHY>, + <&cmu CLK_USB3_CCE>, + <&cmu CLK_USB3_MAC>; + clock-names = "usb3_480mpll0", "usb3_480mphy0", + "usb3_5gphy", "usb3_cce", + "usb3_mac"; + resets = <&cmu RESET_USB3>; + reset-names = "usb3"; + power-domains = <&sps S900_PD_USB3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3_0: dwc3 { + compatible = "snps,dwc3"; + reg = <0x0 0xe0400000 0x0 0xcd00>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; +// phys = <&usb2_phy>, <&usb3_phy>; + usb-phy = <&usb2_phy>, <&usb3_phy>; +// phy-names = "usb2-phy", "usb3-phy"; +// phy_type = "utmi_wide"; + dr_mode = "host"; + power-domains = <&sps S900_PD_USB3>; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; + status = "disabled"; + }; + }; + + usb2_phy: usb2phy@0xe040cd0c { + compatible = "actions,s900-usb2phy"; + reg = <0 0xe040cd0c 0 0x4>; + }; + + usb3_phy: usb3phy@0xe040cf00 { + compatible = "actions,s900-usb3phy"; + reg = <0 0xe040cf00 0 0x100>; + }; }; }; |