path: root/arch/riscv/include/asm/cacheflush.h
diff options
authorAndrew Waterman <andrew@sifive.com>2017-10-25 14:32:16 -0700
committerPalmer Dabbelt <palmer@sifive.com>2017-11-30 12:58:29 -0800
commit921ebd8f2c081b3cf6c3b29ef4103eef3ff26054 (patch)
treee3302d6371f434b91b4194da53342095c68363dd /arch/riscv/include/asm/cacheflush.h
parent08f051eda33b51e8ee0f45f05bcfe49d0f0caf6b (diff)
RISC-V: Allow userspace to flush the instruction cache
Despite RISC-V having a direct 'fence.i' instruction available to userspace (which we can't trap!), that's not actually viable when running on Linux because the kernel might schedule a process on another hart. There is no way for userspace to handle this without invoking the kernel (as it doesn't know the thread->hart mappings), so we've defined a RISC-V specific system call to flush the instruction cache. This patch adds both a system call and a VDSO entry. If possible, we'd like to avoid having the system call be considered part of the user-facing ABI and instead restrict that to the VDSO entry -- both just in general to avoid having additional user-visible ABI to maintain, and because we'd prefer that users just call the VDSO entry because there might be a better way to do this in the future (ie, one that doesn't require entering the kernel). Signed-off-by: Andrew Waterman <andrew@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/include/asm/cacheflush.h')
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
index 5c9ed39ee2a2..efd89a88d2d0 100644
--- a/arch/riscv/include/asm/cacheflush.h
+++ b/arch/riscv/include/asm/cacheflush.h
@@ -52,4 +52,10 @@ void flush_icache_mm(struct mm_struct *mm, bool local);
#endif /* CONFIG_SMP */
+ * Bits in sys_riscv_flush_icache()'s flags argument.
+ */