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authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2019-05-06 17:27:09 +0530
committerManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2019-05-06 17:31:46 +0530
commit6d66ba502b3e1d37c63603f177146a3b1daf1293 (patch)
tree5d10c0e38daea308bdd476338b2744845ceecc52
parenta3c89034a3287d1747ca06f7d99323d3739edc51 (diff)
download96b-common-6d66ba502b3e1d37c63603f177146a3b1daf1293.tar.gz
arm64: dts: rockchip: Enable SPI1 on Ficusrock960_spi
Enable SPI1 exposed on both Low and High speed expansion connectors of Ficus. SPI1 has 3 different chip selects wired as below: CS0 - Serial Flash (unpopulated) CS1 - Low Speed expansion CS2 - High Speed expansion Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-ficus.dts6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
index 027d428917b8..9baa378fc770 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
@@ -146,6 +146,12 @@
};
};
+&spi1 {
+ /* On both Low speed and High speed expansion */
+ cs-gpios = <0>, <&gpio4 6 0>, <&gpio4 7 0>;
+ status = "okay";
+};
+
&usbdrd_dwc3_0 {
dr_mode = "host";
};