aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorShunqian Zheng <zhengsq@rock-chips.com>2018-03-08 17:48:06 +0800
committerManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2019-05-03 11:31:29 +0530
commit557135f7b8e4fa23c0aeac0a7a407662d9324d22 (patch)
tree7f5a3f56ddc1c26972c7b1947ec927799ea416dd
parent41f02d82f5a350108cf5438b0d6569fcf3d0488d (diff)
download96b-common-557135f7b8e4fa23c0aeac0a7a407662d9324d22.tar.gz
arm64: dts: rockchip: add rx0 mipi-phy for rk3399
It's a Designware MIPI D-PHY, used for ISP0 in rk3399. Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 6e9842a074b3..d627217b5cbb 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1381,6 +1381,16 @@
status = "disabled";
};
+ mipi_dphy_rx0: mipi-dphy-rx0 {
+ compatible = "rockchip,rk3399-mipi-dphy";
+ clocks = <&cru SCLK_MIPIDPHY_REF>,
+ <&cru SCLK_DPHY_RX0_CFG>,
+ <&cru PCLK_VIO_GRF>;
+ clock-names = "dphy-ref", "dphy-cfg", "grf";
+ power-domains = <&power RK3399_PD_VIO>;
+ status = "disabled";
+ };
+
u2phy0: usb2-phy@e450 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe450 0x10>;