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author | Jacob Chen <jacob2.chen@rock-chips.com> | 2018-03-08 17:48:01 +0800 |
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committer | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2019-05-03 11:31:29 +0530 |
commit | 07f6a935ed94b074ac3f465084fdfd7e9b6d25ae (patch) | |
tree | 953e16d00b35622c0c8c7965d7c5fbe969eb5ed0 | |
parent | 17683f258896e6a73dbefafebc74b57a562d6a1e (diff) | |
download | 96b-common-07f6a935ed94b074ac3f465084fdfd7e9b6d25ae.tar.gz |
dt-bindings: Document the Rockchip MIPI RX D-PHY bindings
Add DT bindings documentation for Rockchip MIPI D-PHY RX
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-rw-r--r-- | Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt b/Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt new file mode 100644 index 000000000000..d83700faf4c4 --- /dev/null +++ b/Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt @@ -0,0 +1,90 @@ +Rockchip SoC MIPI RX D-PHY +------------------------------------------------------------- + +Required properties: +- compatible: value should be one of the following + "rockchip,rk3288-mipi-dphy" + "rockchip,rk3399-mipi-dphy" +- clocks : list of clock specifiers, corresponding to entries in + clock-names property; +- clock-names: required clock name. + +MIPI RX D-PHY use registers in "general register files", it +should be a child of the GRF. +MIPI TXRX D-PHY have its own registers, it must have a reg property. + +Optional properties: +- reg: offset and length of the register set for the device. +- rockchip,grf: MIPI TX1RX1 D-PHY not only has its own register but also + the GRF, so it is only necessary for MIPI TX1RX1 D-PHY. + +port node +------------------- + +The device node should contain two 'port' child nodes, according to the bindings +defined in Documentation/devicetree/bindings/media/video-interfaces.txt. + +The first port show the sensors connected in this mipi-dphy. +- endpoint: + - remote-endpoint: Linked to a sensor with a MIPI CSI-2 video bus. + - data-lanes : (required) an array specifying active physical MIPI-CSI2 + data input lanes and their mapping to logical lanes; the + D-PHY can't reroute lanes, so the array's content should + be consecutive and only its length is meaningful. + +The port node must contain at least one endpoint. It could have multiple endpoints +linked to different sensors, but please note that they are not supposed to be +activated at the same time. + +The second port should be connected to isp node. +- endpoint: + - remote-endpoint: Linked to Rockchip ISP1, which is defined + in rockchip-isp1.txt. + +Device node example +------------------- + +grf: syscon@ff770000 { + compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; + +... + + mipi_dphy_rx0: mipi-dphy-rx0 { + compatible = "rockchip,rk3399-mipi-dphy"; + clocks = <&cru SCLK_MIPIDPHY_REF>, + <&cru SCLK_DPHY_RX0_CFG>, + <&cru PCLK_VIO_GRF>; + clock-names = "dphy-ref", "dphy-cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_wcam: endpoint@0 { + reg = <0>; + remote-endpoint = <&wcam_out>; + data-lanes = <1 2>; + }; + mipi_in_ucam: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out>; + data-lanes = <1>; + }; + }; + + port@1 { + reg = <1>; + + dphy_rx0_out: endpoint { + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; + }; +}; |