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authorLi Wei <liwei213@huawei.com>2018-01-06 17:51:14 +0800
committerRiku Voipio <riku.voipio@linaro.org>2018-02-12 12:54:19 +0200
commitb09688d991b4743c252e14b696bcc208a1d538b2 (patch)
treec46688cd5f567d2acfbc9732175e34e1d5b46997
parent198eebc0480a69e40b19de89404188311aa23b1a (diff)
download96b-common-b09688d991b4743c252e14b696bcc208a1d538b2.tar.gz
dt-bindings: scsi: ufs: add document for hisi-ufs
add ufs node document for Hisilicon. Signed-off-by: Li Wei <liwei213@huawei.com> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
-rw-r--r--Documentation/devicetree/bindings/ufs/ufs-hisi.txt43
1 files changed, 43 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt
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+* Hisilicon Universal Flash Storage (UFS) Host Controller
+
+UFS nodes are defined to describe on-chip UFS hardware macro.
+Each UFS Host Controller should have its own node.
+
+Required properties:
+- compatible : compatible list, contains one of the following -
+ "hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs
+ host controller present on Hi36xx chipset.
+- reg : should contain UFS register address space & UFS SYS CTRL register address,
+- interrupt-parent : interrupt device
+- interrupts : interrupt number
+- clocks : List of phandle and clock specifier pairs
+- clock-names : List of clock input name strings sorted in the same
+ order as the clocks property. "ref_clk", "phy_clk" is optional
+- freq-table-hz : Array of <min max> operating frequencies stored in the same
+ order as the clocks property. If this property is not
+ defined or a value in the array is "0" then it is assumed
+ that the frequency is set by the parent clock or a
+ fixed rate clock source.
+- resets : reset node register, one reset the clk and the other reset the controller
+- reset-names : describe reset node register
+
+Example:
+
+ ufs: ufs@ff3b0000 {
+ compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
+ /* 0: HCI standard */
+ /* 1: UFS SYS CTRL */
+ reg = <0x0 0xff3b0000 0x0 0x1000>,
+ <0x0 0xff3b1000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
+ clock-names = "ref_clk", "phy_clk";
+ freq-table-hz = <0 0>, <0 0>;
+ /* offset: 0x84; bit: 12 */
+ /* offset: 0x84; bit: 7 */
+ resets = <&crg_rst 0x84 12>,
+ <&crg_rst 0x84 7>;
+ reset-names = "rst", "assert";
+ };