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| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2018-11-02 12:08:33 +0530 |
|---|---|---|
| committer | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2018-11-20 14:07:00 +0530 |
| commit | 7b9be3d2747bcc65225010574e7556d827a7698c (patch) | |
| tree | 6aaf14fa4f63e90fe179ad5c6965535b49b94221 | |
| parent | 5743172d2084e4b49073ca3b9a61858708787250 (diff) | |
| download | 96b-common-7b9be3d2747bcc65225010574e7556d827a7698c.tar.gz | |
arm64: dts: hisilicon: hi3660: Add HiSi ISP
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
| -rw-r--r-- | arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index c694a340bb5f..4c46490d3013 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -266,6 +266,51 @@ hisi,rst-syscon = <&crg_ctrl>; }; + hisi_isp: isp@e8400000 { + compatible = "hisilicon,hisi-isp"; + reg = <0x0 0xe8402000 0x0 0x1000>, + <0x0 0xe8403000 0x0 0x1000>, + <0x0 0xe8406000 0x0 0x1000>, + <0x0 0xe8420000 0x0 0x1000>, + <0x0 0xe8421000 0x0 0x1000>, + <0x0 0xe8422000 0x0 0x1000>, + <0x0 0xe842c000 0x0 0x1000>, + <0x0 0xe842e000 0x0 0x1000>, + <0x0 0xe8583000 0x0 0x1000>; + reg-names = "csi0", "csi1", "smmu_ctrl", "ispss_ctrl", + "sr", "cvdr_rt", "irq_merger2", "cvdr_srt", + "sub_ctrl"; + interrupts = <0 262 4>, <0 266 4>; + interrupt-names = "isp_vic1", "isp_frproc0"; + pinctrl-names = "default"; + pinctrl-0 = <&isp0_pmx_func &isp1_pmx_func + &isp0_cfg_func &isp1_cfg_func + &cam0_rst_pmx_func &cam1_rst_pmx_func + &cam0_rst_cfg_func &cam1_rst_cfg_func + &csi0_pwd_n_pmx_func + &csi1_pwd_n_pmx_func + &csi0_pwd_n_cfg_func + &csi1_pwd_n_cfg_func>; + clocks = <&crg_ctrl HI3660_CLK_GATE_ISP_SNCLK0>, + <&crg_ctrl HI3660_CLK_GATE_ISP_SNCLK1>; + clock-names = "isp_snclk0", "isp_snclk1"; + clock-rates = <24000000>; + pool-size = <0x1000000>; + status = "ok"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csiphy0_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 2>; + remote-endpoint = <&ov5645_ep>; + }; + }; + }; + }; pctrl: pctrl@e8a09000 { compatible = "hisilicon,hi3660-pctrl", "syscon"; |