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authorXu YiPing <xuyiping@hisilicon.com>2017-11-09 19:18:23 +0800
committerRiku Voipio <riku.voipio@linaro.org>2018-02-12 12:54:18 +0200
commit6aaf353b65c0a750cc654653d214858e125f8900 (patch)
treefe777e237ca583a0ddcce4150893974ff02fefb2
parent49165e0b0209628b642071546809361998f2d556 (diff)
download96b-common-6aaf353b65c0a750cc654653d214858e125f8900.tar.gz
arm64: dts: hi3660: improve pmu description
cortex-a73 pmu driver is supported now. hi3660 is 4*a73 + 4*a53, so it should use "cortex-a73-pmu" and "cortex-a53-pmu" instead of "armpmu-v3", then we can use the a73 and a53 events in perf tool directly. Signed-off-by: Xu YiPing <xuyiping@hisilicon.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi3660.dtsi22
1 files changed, 13 insertions, 9 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index ab0b95ba5ae5..723adb107c0d 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -203,21 +203,25 @@
IRQ_TYPE_LEVEL_HIGH)>;
};
- pmu {
- compatible = "arm,armv8-pmuv3";
+ a53-pmu {
+ compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
- <&cpu3>,
- <&cpu4>,
+ <&cpu3>;
+ };
+
+ a73-pmu {
+ compatible = "arm,cortex-a73-pmu";
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu4>,
<&cpu5>,
<&cpu6>,
<&cpu7>;