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authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2018-08-19 14:06:05 +0530
committerManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2018-08-19 14:39:20 +0530
commit864c8d9fba0f13a09473937f81244f6da02b8213 (patch)
tree53fb14578e1778fb07b8dd705ba6450913f480b0
parentf0dda00a0710d37e07f64595eeff98b785ae5de6 (diff)
download96b-common-864c8d9fba0f13a09473937f81244f6da02b8213.tar.gz
arm64: dts: hisilicon: Add clock nodes for Hi3670 SoC
Add clock nodes for HiSilicon Hi3670 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi3670.dtsi43
1 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index c90e6f6a34ec..8a0ee4b08886 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -7,6 +7,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/hi3670-clock.h>
/ {
compatible = "hisilicon,hi3670";
@@ -144,6 +145,48 @@
#size-cells = <2>;
ranges;
+ crg_ctrl: crg_ctrl@fff35000 {
+ compatible = "hisilicon,hi3670-crgctrl", "syscon";
+ reg = <0x0 0xfff35000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pctrl: pctrl@e8a09000 {
+ compatible = "hisilicon,hi3670-pctrl", "syscon";
+ reg = <0x0 0xe8a09000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pmuctrl: crg_ctrl@fff34000 {
+ compatible = "hisilicon,hi3670-pmuctrl", "syscon";
+ reg = <0x0 0xfff34000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sctrl: sctrl@fff0a000 {
+ compatible = "hisilicon,hi3670-sctrl", "syscon";
+ reg = <0x0 0xfff0a000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ iomcu: iomcu@ffd7e000 {
+ compatible = "hisilicon,hi3670-iomcu", "syscon";
+ reg = <0x0 0xffd7e000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ media1_crg: media1_crgctrl@e87ff000 {
+ compatible = "hisilicon,hi3670-media1-crg", "syscon";
+ reg = <0x0 0xe87ff000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ media2_crg: media2_crgctrl@e8900000 {
+ compatible = "hisilicon,hi3670-media2-crg","syscon";
+ reg = <0x0 0xe8900000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
uart6_clk: clk_19_2M {
compatible = "fixed-clock";
#clock-cells = <0>;