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authorJacob Chen <jacob2.chen@rock-chips.com>2018-03-08 17:48:03 +0800
committerManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2019-05-03 11:31:29 +0530
commite472f696c1c8c051a8e6d282be686e2425ea1c15 (patch)
tree0691e083c3948a73491fee45421e1d62c054caec
parent5d9f4d031e4675926ef0d537a4c677ddd7c1196c (diff)
download96b-common-e472f696c1c8c051a8e6d282be686e2425ea1c15.tar.gz
ARM: dts: rockchip: add rx0 mipi-phy for rk3288
It's a Designware MIPI D-PHY, used by ISP in rk3288. Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-rw-r--r--arch/arm/boot/dts/rk3288.dtsi7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 65c4b99ba379..ab4fe1a4447e 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -887,6 +887,13 @@
status = "disabled";
};
+ mipi_phy_rx0: mipi-phy-rx0 {
+ compatible = "rockchip,rk3288-mipi-dphy";
+ clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_CSI>;
+ clock-names = "dphy-ref", "pclk";
+ status = "disabled";
+ };
+
io_domains: io-domains {
compatible = "rockchip,rk3288-io-voltage-domain";
status = "disabled";