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authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2019-05-07 20:12:43 +0530
committerManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2019-05-07 22:16:16 +0530
commitc7a62a9f9227c903075bba47386d4baa49416fd9 (patch)
tree92ff48e20ef59e42a9406a14f5ecea4d21e5886a
parent9c8f412dc7a74ca8f10d4f6ff10a275208334e56 (diff)
download96b-common-c7a62a9f9227c903075bba47386d4baa49416fd9.tar.gz
temp
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi143
-rw-r--r--drivers/media/platform/Kconfig1
-rw-r--r--drivers/media/platform/rockchip/isp1/capture.c18
-rw-r--r--drivers/media/platform/rockchip/isp1/dev.c8
-rw-r--r--drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c8
-rw-r--r--drivers/media/platform/rockchip/isp1/rkisp1.c24
6 files changed, 170 insertions, 32 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
index 2927db4dda9d..3fb499da039e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (c) 2018 Collabora Ltd.
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
@@ -66,6 +66,30 @@
regulator-always-on;
vin-supply = <&vcc_sys>;
};
+
+ camera_vdddo_1v8: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera_vdddo";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ camera_vdda_2v8: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera_vdda";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ camera_vddd_1v5: fixedregulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera_vddd";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
};
&cpu_l0 {
@@ -339,6 +363,32 @@
&i2c2 {
status = "okay";
+
+ camera0: ov5645@3c {
+ compatible = "ovti,ov5645";
+ reg = <0x3c>;
+ clocks = <&cru SCLK_CIF_OUT>;
+ clock-names = "xclk";
+ clock-frequency = <24000000>;
+
+ vdddo-supply = <&camera_vdddo_1v8>;
+ vdda-supply = <&camera_vdda_2v8>;
+ vddd-supply = <&camera_vddd_1v5>;
+ pinctrl-0 = <&cam0_default_pins>;
+ pinctrl-names = "default";
+ enable-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+
+ status = "disabled";
+/*
+ port {
+ ov5645_0_out: endpoint {
+ remote-endpoint = <&ov5645_0_in>;
+ clock-lanes = <1>;
+ data-lanes = <1 2>;
+ };
+ };
+*/ };
};
&i2c3 {
@@ -349,6 +399,33 @@
status = "okay";
};
+&i2c6 {
+ status = "okay";
+
+ camera1: ov5645@3c {
+ compatible = "ovti,ov5645";
+ reg = <0x3c>;
+ clocks = <&cru SCLK_CIF_OUT>;
+ clock-names = "xclk";
+ clock-frequency = <24000000>;
+
+ vdddo-supply = <&camera_vdddo_1v8>;
+ vdda-supply = <&camera_vdda_2v8>;
+ vddd-supply = <&camera_vddd_1v5>;
+ pinctrl-0 = <&cam0_default_pins>;
+ pinctrl-names = "default";
+ enable-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_LOW>;
+
+ port {
+ ov5645_1_out: endpoint {
+ remote-endpoint = <&ov5645_1_in>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
&i2s2 {
status = "okay";
};
@@ -467,6 +544,19 @@
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ cam_pins {
+ cam_pwr: cam-pwr {
+ rockchip,pins = <4 4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ cam0_default_pins: cam0-default-pins {
+ rockchip,pins =
+ <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
+ <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>,
+ <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
+ <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&pwm2 {
@@ -636,3 +726,54 @@
&vopl_mmu {
status = "okay";
};
+
+&isp0_mmu {
+ status = "okay";
+};
+
+&isp1_mmu {
+ status = "okay";
+};
+
+&isp0 {
+ status = "okay";
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ isp_mipi_in: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dphy_rx0_out>;
+ };
+ };
+};
+
+&mipi_dphy_rx0 {
+ status = "okay";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+/*
+ port@0 {
+ reg = <0>;
+ ov5645_0_in: endpoint {
+ remote-endpoint = <&ov5645_0_out>;
+ data-lanes = <1 2>;
+ };
+ };
+*/
+ port@0 {
+ reg = <0>;
+ ov5645_1_in: endpoint {
+ remote-endpoint = <&ov5645_1_out>;
+ data-lanes = <1 2>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dphy_rx0_out: endpoint {
+ remote-endpoint = <&isp_mipi_in>;
+ };
+ };
+ };
+};
diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 851a12487503..a1269abdf5e9 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -111,6 +111,7 @@ config VIDEO_ROCKCHIP_ISP1
depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
depends on ARCH_ROCKCHIP || COMPILE_TEST
select VIDEOBUF2_DMA_CONTIG
+ select VIDEOBUF2_VMALLOC
select V4L2_FWNODE
default n
---help---
diff --git a/drivers/media/platform/rockchip/isp1/capture.c b/drivers/media/platform/rockchip/isp1/capture.c
index 53484f882704..b44a057ca553 100644
--- a/drivers/media/platform/rockchip/isp1/capture.c
+++ b/drivers/media/platform/rockchip/isp1/capture.c
@@ -635,14 +635,14 @@ static int rkisp1_config_dcrop(struct rkisp1_stream *stream, bool async)
dcrop->height == input_win->height &&
dcrop->left == 0 && dcrop->top == 0) {
disable_dcrop(stream, async);
- v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
+ v4l2_dbg(1, 1, &dev->v4l2_dev,
"stream %d crop disabled\n", stream->id);
return 0;
}
config_dcrop(stream, dcrop, async);
- v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
+ v4l2_dbg(1, 1, &dev->v4l2_dev,
"stream %d crop: %dx%d -> %dx%d\n", stream->id,
input_win->width, input_win->height,
dcrop->width, dcrop->height);
@@ -691,18 +691,18 @@ static int rkisp1_config_rsz(struct rkisp1_stream *stream, bool async)
goto disable;
/* set RSZ input and output */
- v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
+ v4l2_dbg(1, 1, &dev->v4l2_dev,
"stream %d rsz/scale: %dx%d -> %dx%d\n",
stream->id, stream->dcrop.width, stream->dcrop.height,
output_fmt.width, output_fmt.height);
- v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
+ v4l2_dbg(1, 1, &dev->v4l2_dev,
"chroma scaling %dx%d -> %dx%d\n",
in_c.width, in_c.height, out_c.width, out_c.height);
/* calculate and set scale */
config_rsz(stream, &in_y, &in_c, &out_y, &out_c, async);
- if (rkisp1_debug)
+ if (1)
dump_rsz_regs(stream);
return 0;
@@ -835,7 +835,7 @@ static void update_mi(struct rkisp1_stream *stream)
mi_set_cr_addr(stream,
stream->next_buf->buff_addr[RKISP1_PLANE_CR]);
} else {
- v4l2_dbg(1, rkisp1_debug, &stream->ispdev->v4l2_dev,
+ v4l2_dbg(1, 1, &stream->ispdev->v4l2_dev,
"stream %d: to dummy buf\n", stream->id);
mi_set_y_addr(stream, dummy_buf->dma_addr);
mi_set_cb_addr(stream, dummy_buf->dma_addr);
@@ -1023,7 +1023,7 @@ static int rkisp1_queue_setup(struct vb2_queue *queue,
sizes[i] = plane_fmt->sizeimage;
}
- v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev, "%s count %d, size %d\n",
+ v4l2_dbg(1, 1, &dev->v4l2_dev, "%s count %d, size %d\n",
v4l2_type_names[queue->type], *num_buffers, sizes[0]);
return 0;
@@ -1373,7 +1373,7 @@ static void rkisp1_set_fmt(struct rkisp1_stream *stream,
} else {
stream->u.mp.raw_enable = (fmt->fmt_type == FMT_BAYER);
}
- v4l2_dbg(1, rkisp1_debug, &stream->ispdev->v4l2_dev,
+ v4l2_dbg(1, 1, &stream->ispdev->v4l2_dev,
"%s: stream: %d req(%d, %d) out(%d, %d)\n", __func__,
stream->id, pixm->width, pixm->height,
stream->out_fmt.width, stream->out_fmt.height);
@@ -1586,7 +1586,7 @@ static int rkisp1_s_selection(struct file *file, void *prv,
if (sel->target == V4L2_SEL_TGT_CROP) {
*dcrop = *rkisp1_update_crop(stream, &sel->r, input_win);
- v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
+ v4l2_dbg(1, 1, &dev->v4l2_dev,
"stream %d crop(%d,%d)/%dx%d\n", stream->id,
dcrop->left, dcrop->top, dcrop->width, dcrop->height);
}
diff --git a/drivers/media/platform/rockchip/isp1/dev.c b/drivers/media/platform/rockchip/isp1/dev.c
index 990ac28e4107..17d662846304 100644
--- a/drivers/media/platform/rockchip/isp1/dev.c
+++ b/drivers/media/platform/rockchip/isp1/dev.c
@@ -21,7 +21,7 @@ struct isp_match_data {
int size;
};
-int rkisp1_debug;
+int rkisp1_debug = 1;
module_param_named(debug, rkisp1_debug, int, 0644);
MODULE_PARM_DESC(debug, "Debug level (0-1)");
@@ -292,7 +292,7 @@ static int subdev_notifier_bound(struct v4l2_async_notifier *notifier,
isp_dev->sensors[isp_dev->num_sensors].sd = subdev;
++isp_dev->num_sensors;
- v4l2_dbg(1, rkisp1_debug, subdev, "Async registered subdev\n");
+ v4l2_dbg(1, 1, subdev, "Async registered subdev\n");
return 0;
}
@@ -330,15 +330,13 @@ static int isp_subdev_notifier(struct rkisp1_device *isp_dev)
struct device *dev = isp_dev->dev;
int ret;
+ v4l2_async_notifier_init(ntf);
ret = v4l2_async_notifier_parse_fwnode_endpoints(
dev, ntf, sizeof(struct rkisp1_async_subdev),
rkisp1_fwnode_parse);
if (ret < 0)
return ret;
- if (!ntf->num_subdevs)
- return -ENODEV; /* no endpoint */
-
ntf->ops = &subdev_notifier_ops;
return v4l2_async_notifier_register(&isp_dev->v4l2_dev, ntf);
diff --git a/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
index 32140960557a..100c2e397560 100644
--- a/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
+++ b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
@@ -697,7 +697,7 @@ static int rockchip_mipidphy_fwnode_parse(struct device *dev,
container_of(asd, struct sensor_async_subdev, asd);
struct v4l2_mbus_config *config = &s_asd->mbus;
- if (vep->bus_type != V4L2_MBUS_CSI2) {
+ if (vep->bus_type != V4L2_MBUS_CSI2_DPHY) {
dev_err(dev, "Only CSI2 bus type is currently supported\n");
return -EINVAL;
}
@@ -707,7 +707,7 @@ static int rockchip_mipidphy_fwnode_parse(struct device *dev,
return -EINVAL;
}
- config->type = V4L2_MBUS_CSI2;
+ config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = vep->bus.mipi_csi2.flags;
s_asd->lanes = vep->bus.mipi_csi2.num_data_lanes;
@@ -745,6 +745,7 @@ static int rockchip_mipidphy_media_init(struct mipidphy_priv *priv)
if (ret < 0)
return ret;
+ v4l2_async_notifier_init(&priv->notifier);
ret = v4l2_async_notifier_parse_fwnode_endpoints_by_port(
priv->dev, &priv->notifier,
sizeof(struct sensor_async_subdev), 0,
@@ -752,9 +753,6 @@ static int rockchip_mipidphy_media_init(struct mipidphy_priv *priv)
if (ret < 0)
return ret;
- if (!priv->notifier.num_subdevs)
- return -ENODEV; /* no endpoint */
-
priv->sd.subdev_notifier = &priv->notifier;
priv->notifier.ops = &rockchip_mipidphy_async_ops;
ret = v4l2_async_subdev_notifier_register(&priv->sd, &priv->notifier);
diff --git a/drivers/media/platform/rockchip/isp1/rkisp1.c b/drivers/media/platform/rockchip/isp1/rkisp1.c
index bb16c8118c16..2c617a672dd0 100644
--- a/drivers/media/platform/rockchip/isp1/rkisp1.c
+++ b/drivers/media/platform/rockchip/isp1/rkisp1.c
@@ -153,7 +153,7 @@ static int rkisp1_config_isp(struct rkisp1_device *dev)
}
} else if (in_fmt->fmt_type == FMT_YUV) {
acq_mult = 2;
- if (sensor->mbus.type == V4L2_MBUS_CSI2) {
+ if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
isp_ctrl = CIF_ISP_CTRL_ISP_MODE_ITU601;
} else {
if (sensor->mbus.type == V4L2_MBUS_BT656)
@@ -290,7 +290,7 @@ static int rkisp1_config_mipi(struct rkisp1_device *dev)
CIF_MIPI_SYNC_FIFO_OVFLW(0x03) | CIF_MIPI_ADD_DATA_OVFLW,
base + CIF_MIPI_IMSC);
- v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev, "\n MIPI_CTRL 0x%08x\n"
+ v4l2_dbg(1, 1, &dev->v4l2_dev, "\n MIPI_CTRL 0x%08x\n"
" MIPI_IMG_DATA_SEL 0x%08x\n"
" MIPI_STATUS 0x%08x\n"
" MIPI_IMSC 0x%08x\n",
@@ -313,7 +313,7 @@ static int rkisp1_config_path(struct rkisp1_device *dev)
sensor->mbus.type == V4L2_MBUS_PARALLEL) {
ret = rkisp1_config_dvp(dev);
dpcl |= CIF_VI_DPCL_IF_SEL_PARALLEL;
- } else if (sensor->mbus.type == V4L2_MBUS_CSI2) {
+ } else if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
ret = rkisp1_config_mipi(dev);
dpcl |= CIF_VI_DPCL_IF_SEL_MIPI;
}
@@ -329,13 +329,13 @@ static int rkisp1_config_cif(struct rkisp1_device *dev)
int ret = 0;
u32 cif_id;
- v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
+ v4l2_dbg(1, 1, &dev->v4l2_dev,
"SP state = %d, MP state = %d\n",
dev->stream[RKISP1_STREAM_SP].state,
dev->stream[RKISP1_STREAM_MP].state);
cif_id = readl(dev->base_addr + CIF_VI_ID);
- v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev, "CIF_ID 0x%08x\n", cif_id);
+ v4l2_dbg(1, 1, &dev->v4l2_dev, "CIF_ID 0x%08x\n", cif_id);
ret = rkisp1_config_isp(dev);
if (ret < 0)
@@ -354,7 +354,7 @@ static int rkisp1_isp_stop(struct rkisp1_device *dev)
void __iomem *base = dev->base_addr;
u32 val;
- v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
+ v4l2_dbg(1, 1, &dev->v4l2_dev,
"SP state = %d, MP state = %d\n",
dev->stream[RKISP1_STREAM_SP].state,
dev->stream[RKISP1_STREAM_MP].state);
@@ -384,7 +384,7 @@ static int rkisp1_isp_stop(struct rkisp1_device *dev)
readx_poll_timeout(readl, base + CIF_ISP_RIS,
val, val & CIF_ISP_OFF, 20, 100);
- v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
+ v4l2_dbg(1, 1, &dev->v4l2_dev,
"state(MP:%d, SP:%d), MI_CTRL:%x, ISP_CTRL:%x, MIPI_CTRL:%x\n",
dev->stream[RKISP1_STREAM_SP].state,
dev->stream[RKISP1_STREAM_MP].state,
@@ -405,13 +405,13 @@ static int rkisp1_isp_start(struct rkisp1_device *dev)
void __iomem *base = dev->base_addr;
u32 val;
- v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
+ v4l2_dbg(1, 1, &dev->v4l2_dev,
"SP state = %d, MP state = %d\n",
dev->stream[RKISP1_STREAM_SP].state,
dev->stream[RKISP1_STREAM_MP].state);
/* Activate MIPI */
- if (sensor->mbus.type == V4L2_MBUS_CSI2) {
+ if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
val = readl(base + CIF_MIPI_CTRL);
writel(val | CIF_MIPI_CTRL_OUTPUT_ENA, base + CIF_MIPI_CTRL);
}
@@ -427,7 +427,7 @@ static int rkisp1_isp_start(struct rkisp1_device *dev)
*/
usleep_range(1000, 1200);
- v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
+ v4l2_dbg(1, 1, &dev->v4l2_dev,
"SP state = %d, MP state = %d MI_CTRL 0x%08x\n"
" ISP_CTRL 0x%08x MIPI_CTRL 0x%08x\n",
dev->stream[RKISP1_STREAM_SP].state,
@@ -845,7 +845,7 @@ static int rkisp1_isp_sd_set_selection(struct v4l2_subdev *sd,
if (sel->target != V4L2_SEL_TGT_CROP)
return -EINVAL;
- v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
+ v4l2_dbg(1, 1, &dev->v4l2_dev,
"%s: pad: %d sel(%d,%d)/%dx%d\n", __func__, sel->pad,
sel->r.left, sel->r.top, sel->r.width, sel->r.height);
rkisp1_isp_sd_try_crop(sd, cfg, sel);
@@ -904,7 +904,7 @@ static int rkisp1_isp_sd_s_power(struct v4l2_subdev *sd, int on)
struct rkisp1_device *isp_dev = sd_to_isp_dev(sd);
int ret;
- v4l2_dbg(1, rkisp1_debug, &isp_dev->v4l2_dev, "s_power: %d\n", on);
+ v4l2_dbg(1, 1, &isp_dev->v4l2_dev, "s_power: %d\n", on);
if (on) {
ret = pm_runtime_get_sync(isp_dev->dev);