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authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2019-05-14 23:16:15 +0530
committerManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2019-05-14 23:16:15 +0530
commit3019664a30cce93c87de7f1e828a29795acbb3c7 (patch)
tree140fc7cf859417ceb3b4ea7ef3e142cb7a13ae4a
parent76aa8fc6d5afdfb97545265ffbdcbb412cba7670 (diff)
download96b-common-3019664a30cce93c87de7f1e828a29795acbb3c7.tar.gz
dt-bindings: clock: Add devicetree binding for BM1880 SoC
Add devicetree binding for Bitmain BM1880 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-rw-r--r--Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt38
-rw-r--r--include/dt-bindings/clock/bm1880-clock.h66
2 files changed, 104 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt
new file mode 100644
index 000000000000..aa8468329ab5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt
@@ -0,0 +1,38 @@
+* Bitmain BM1880 Clock Controller
+
+The Bitmain BM1880 clock controler generates and supplies clock to
+various peripherals within the SoC.
+
+Required Properties:
+
+- compatible: Should be "bitmain,bm1880-clk"
+- reg: Offset and length of clock controller space in SCTRL.
+- #clock-cells: Should be 1.
+
+Each clock is assigned an identifier, and client nodes can use this identifier
+to specify the clock which they consume.
+
+All available clocks are defined as preprocessor macros in corresponding
+dt-bindings/clock/bm1880-clock.h header and can be used in device tree sources.
+
+Example:
+
+ clk: clock-controller@800 {
+ compatible = "bitmain,bm1880-clk";
+ reg = <0x800 0x8>;
+ #clock-cells = <1>;
+ };
+
+Example: UART controller node that consumes clock generated by the clock
+controller:
+
+ uart0: serial@58018000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x58018000 0x0 0x2000>;
+ clocks = <&clk BM1880_CLK_UART_500M>;
+ <&clk BM1880_CLK_APB_UART>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
diff --git a/include/dt-bindings/clock/bm1880-clock.h b/include/dt-bindings/clock/bm1880-clock.h
new file mode 100644
index 000000000000..de19d7b167f8
--- /dev/null
+++ b/include/dt-bindings/clock/bm1880-clock.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Device Tree binding constants for Bitmain BM1880 SoC
+ *
+ * Copyright (c) 2019 Linaro Ltd.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BM1880_H
+#define __DT_BINDINGS_CLOCK_BM1880_H
+
+#define BM1880_CLK_A53 0
+#define BM1880_CLK_50M_A53 1
+#define BM1880_CLK_AHB_ROM 2
+#define BM1880_CLK_AXI_SRAM 3
+#define BM1880_CLK_DDR_AXI 4
+#define BM1880_CLK_EFUSE 5
+#define BM1880_CLK_APB_EFUSE 6
+#define BM1880_CLK_AXI_EMMC 7
+#define BM1880_CLK_EMMC 8
+#define BM1880_CLK_100K_EMMC 9
+#define BM1880_CLK_AXI_SD 10
+#define BM1880_CLK_SD 11
+#define BM1880_CLK_100K_SD 12
+#define BM1880_CLK_500M_ETH0 13
+#define BM1880_CLK_AXI_ETH0 14
+#define BM1880_CLK_500M_ETH1 15
+#define BM1880_CLK_AXI_ETH1 16
+#define BM1880_CLK_AXI_GDMA 17
+#define BM1880_CLK_APB_GPIO 18
+#define BM1880_CLK_APB_GPIO_INTR 19
+#define BM1880_CLK_GPIO_DB 20
+#define BM1880_CLK_AXI_MINER 21
+#define BM1880_CLK_AHB_SF 22
+#define BM1880_CLK_SDMA_AXI 23
+#define BM1880_CLK_SDMA_AUD 24
+#define BM1880_CLK_APB_I2C 25
+#define BM1880_CLK_APB_WDT 26
+#define BM1880_CLK_APB_JPEG 27
+#define BM1880_CLK_JPEG_AXI 28
+#define BM1880_CLK_AXI_NF 29
+#define BM1880_CLK_APB_NF 30
+#define BM1880_CLK_NF 31
+#define BM1880_CLK_APB_PWM 32
+#define BM1880_CLK_RV 33
+#define BM1880_CLK_APB_SPI 34
+#define BM1880_CLK_TPU_AXI 35
+#define BM1880_CLK_UART_500M 36
+#define BM1880_CLK_APB_UART 37
+#define BM1880_CLK_APB_I2S 38
+#define BM1880_CLK_AXI_USB 39
+#define BM1880_CLK_APB_USB 40
+#define BM1880_CLK_125M_USB 41
+#define BM1880_CLK_33K_USB 42
+#define BM1880_CLK_12M_USB 43
+#define BM1880_CLK_APB_VIDEO 44
+#define BM1880_CLK_VIDEO_AXI 45
+#define BM1880_CLK_VPP_AXI 46
+#define BM1880_CLK_APB_VPP 47
+#define BM1880_CLK_AXI1 48
+#define BM1880_CLK_AXI2 49
+#define BM1880_CLK_AXI3 50
+#define BM1880_CLK_AXI4 51
+#define BM1880_CLK_AXI5 52
+#define BM1880_CLK_AXI6 53
+
+#endif /* __DT_BINDINGS_CLOCK_BM1880_H */