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authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2019-04-25 18:09:59 +0530
committerManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2019-05-13 17:07:33 +0530
commit555b2665f2b5a8f71a33b1644cc6ce015dcab099 (patch)
treeb980af88b9a11f48b5a80a504b1fdf05da5fad07
parentc828317468f209e23b45a18640c0de8b1cf609d3 (diff)
download96b-common-555b2665f2b5a8f71a33b1644cc6ce015dcab099.tar.gz
arm64: dts: bitmain: Add reset controller support for BM1880 SoC
Add reset controller support for Bitmain BM1880 SoC. This SoC has two reset controllers, each controlling reset lines of different peripherals. This commit also adds reset support to UART peripherals. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
-rw-r--r--arch/arm64/boot/dts/bitmain/bm1880.dtsi17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
index fdfdc65d29ef..37ecb760a2d2 100644
--- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi
+++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
@@ -5,6 +5,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/bitmain,bm1880-reset.h>
/ {
compatible = "bitmain,bm1880";
@@ -92,6 +93,18 @@
compatible = "bitmain,bm1880-pinctrl";
reg = <0x50 0x4B0>;
};
+
+ clk_rst: reset-controller@800 {
+ compatible = "bitmain,bm1880-reset";
+ reg = <0x800 0x8>;
+ #reset-cells = <1>;
+ };
+
+ rst: reset-controller@C00 {
+ compatible = "bitmain,bm1880-reset";
+ reg = <0xC00 0x8>;
+ #reset-cells = <1>;
+ };
};
uart0: serial@58018000 {
@@ -100,6 +113,7 @@
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst BM1880_RST_UART0_1_CLK>;
status = "disabled";
};
@@ -109,6 +123,7 @@
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst BM1880_RST_UART0_1_ACLK>;
status = "disabled";
};
@@ -118,6 +133,7 @@
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst BM1880_RST_UART2_3_CLK>;
status = "disabled";
};
@@ -127,6 +143,7 @@
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst BM1880_RST_UART2_3_ACLK>;
status = "disabled";
};
};