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authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2019-06-09 00:43:34 +0530
committerManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2019-06-17 20:59:23 +0530
commitc8f51e2a1564279a7a6d4e91be055ec270ecfb34 (patch)
tree922bb07c2dc9f406c19171be9d655dde42199e7a
parentccd583766ae43fce6d721a01965071c8fc895ebe (diff)
download96b-common-c8f51e2a1564279a7a6d4e91be055ec270ecfb34.tar.gz
dt-bindings: mmc: Add Actions Semi SD/MMC/SDIO controller binding
Add devicetree binding for Actions Semi Owl SoC's SD/MMC/SDIO controller. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-rw-r--r--Documentation/devicetree/bindings/mmc/owl-mmc.txt37
1 files changed, 37 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mmc/owl-mmc.txt b/Documentation/devicetree/bindings/mmc/owl-mmc.txt
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+++ b/Documentation/devicetree/bindings/mmc/owl-mmc.txt
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+Actions Semi Owl SoCs SD/MMC/SDIO controller
+
+Required properties:
+- compatible: should be "actions,owl-mmc"
+- reg: offset and length of the register set for the device.
+- interrupts: single interrupt specifier.
+- clocks: single clock specifier of the controller clock.
+- resets: phandle to the reset line.
+- dma-names: should be "mmc".
+- dmas: single DMA channel specifier
+
+Optional properties:
+- pinctrl-names: pinctrl state names "default" must be defined.
+- pinctrl-0: phandle referencing pin configuration of the controller.
+- bus-width: see mmc.txt
+- cap-sd-highspeed: see mmc.txt
+- cap-mmc-highspeed: see mmc.txt
+- sd-uhs-sdr12: see mmc.txt
+- sd-uhs-sdr25: see mmc.txt
+- sd-uhs-sdr50: see mmc.txt
+- non-removable: see mmc.txt
+
+Example:
+
+ mmc0: mmc@e0330000 {
+ compatible = "actions,owl-mmc";
+ reg = <0x0 0xe0330000 0x0 0x4000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_SD0>;
+ resets = <&cmu RESET_SD0>;
+ dmas = <&dma 2>;
+ dma-names = "mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_default>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ };