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authorArd Biesheuvel <ard.biesheuvel@linaro.org>2019-01-31 14:17:18 +0100
committerMarc Zyngier <marc.zyngier@arm.com>2019-02-19 21:05:49 +0000
commit793acf870ea3e492c6bb3edb5f8657d9c4f4903f (patch)
treea9feead9ca8051ec38df14448abe9cd53469f192 /virt
parentf7f2b15c3d42fa5754131b34a0f7ad5a5c3f777f (diff)
downloadlinux-stericsson-793acf870ea3e492c6bb3edb5f8657d9c4f4903f.tar.gz
arm64: KVM: Describe data or unified caches as having 1 set and 1 way
On SMP ARM systems, cache maintenance by set/way should only ever be done in the context of onlining or offlining CPUs, which is typically done by bare metal firmware and never in a virtual machine. For this reason, we trap set/way cache maintenance operations and replace them with conditional flushing of the entire guest address space. Due to this trapping, the set/way arguments passed into the set/way ops are completely ignored, and thus irrelevant. This also means that the set/way geometry is equally irrelevant, and we can simply report it as 1 set and 1 way, so that legacy 32-bit ARM system software (i.e., the kind that only receives odd fixes) doesn't take a performance hit due to the trapping when iterating over the cachelines. Acked-by: Christoffer Dall <christoffer.dall@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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