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authorArnaud Mouiche <arnaud.mouiche@invoxia.com>2016-05-03 14:13:58 +0200
committerMark Brown <broonie@kernel.org>2016-05-13 12:15:31 +0100
commitd9f2a202877c15818d98268f47d6b4bcfcb84437 (patch)
tree19910d1343b8c3f56e89fd2a5b72d3ca48cac430 /sound
parent0096b693962d3abde4f41b13cf03c765f33e9d8d (diff)
downloadlinux-stericsson-d9f2a202877c15818d98268f47d6b4bcfcb84437.tar.gz
ASoC: fsl_ssi: Fix samples being dropped at Playback startup
If the capture is already running while playback is started, it is highly probable (>80% in a 8 channels scenario) that samples are lost between the DMA and TX fifo. The reason is that SIER.TDMAE is set before STCR.TFEN0, leaving a time window where the FIFO doesn't receive the samples written by the DMA. This particular case happened only if capture is already enabled as SCR.SSIEN is already set at the playback startup instant. Signed-off-by: Arnaud Mouiche <arnaud.mouiche@invoxia.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Caleb Crome <caleb@crome.org> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/fsl/fsl_ssi.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 149df3ca4f5e..47ebb835f3f5 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -475,9 +475,9 @@ static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
* (online configuration)
*/
if (enable) {
- regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
+ regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
} else {
u32 sier;
u32 srcr;