|author||Linus Torvalds <email@example.com>||2005-04-16 15:20:36 -0700|
|committer||Linus Torvalds <firstname.lastname@example.org>||2005-04-16 15:20:36 -0700|
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/i386/kernel/cpu/changelog')
1 files changed, 63 insertions, 0 deletions
diff --git a/arch/i386/kernel/cpu/changelog b/arch/i386/kernel/cpu/changelog
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+ * Enhanced CPU type detection by Mike Jagdis, Patrick St. Jean
+ * and Martin Mares, November 1997.
+ * Force Cyrix 6x86(MX) and M II processors to report MTRR capability
+ * and Cyrix "coma bug" recognition by
+ * Zoltán Böszörményi <email@example.com> February 1999.
+ * Force Centaur C6 processors to report MTRR capability.
+ * Bart Hartgers <firstname.lastname@example.org>, May 1999.
+ * Intel Mobile Pentium II detection fix. Sean Gilley, June 1999.
+ * IDT Winchip tweaks, misc clean ups.
+ * Dave Jones <email@example.com>, August 1999
+ * Better detection of Centaur/IDT WinChip models.
+ * Bart Hartgers <firstname.lastname@example.org>, August 1999.
+ * Cleaned up cache-detection code
+ * Dave Jones <email@example.com>, October 1999
+ * Added proper L2 cache detection for Coppermine
+ * Dragan Stancevic <firstname.lastname@example.org>, October 1999
+ * Added the original array for capability flags but forgot to credit
+ * myself :) (~1998) Fixed/cleaned up some cpu_model_info and other stuff
+ * Jauder Ho <email@example.com>, January 2000
+ * Detection for Celeron coppermine, identify_cpu() overhauled,
+ * and a few other clean ups.
+ * Dave Jones <firstname.lastname@example.org>, April 2000
+ * Pentium III FXSR, SSE support
+ * General FPU state handling cleanups
+ * Gareth Hughes <email@example.com>, May 2000
+ * Added proper Cascades CPU and L2 cache detection for Cascades
+ * and 8-way type cache happy bunch from Intel:^)
+ * Dragan Stancevic <firstname.lastname@example.org>, May 2000
+ * Forward port AMD Duron errata T13 from 2.2.17pre
+ * Dave Jones <email@example.com>, August 2000
+ * Forward port lots of fixes/improvements from 2.2.18pre
+ * Cyrix III, Pentium IV support.
+ * Dave Jones <firstname.lastname@example.org>, October 2000
+ * Massive cleanup of CPU detection and bug handling;
+ * Transmeta CPU detection,
+ * H. Peter Anvin <email@example.com>, November 2000
+ * VIA C3 Support.
+ * Dave Jones <firstname.lastname@example.org>, March 2001
+ * AMD Athlon/Duron/Thunderbird bluesmoke support.
+ * Dave Jones <email@example.com>, April 2001.
+ * CacheSize bug workaround updates for AMD, Intel & VIA Cyrix.
+ * Dave Jones <firstname.lastname@example.org>, September, October 2001.