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authorLeif Lindholm <leif.lindholm@linaro.org>2015-04-30 14:45:05 +0100
committerLeif Lindholm <leif.lindholm@linaro.org>2015-05-11 12:05:12 +0100
commit8e01088dfe0ce65d00d1488b6ee08390b3a3bb1a (patch)
tree065b7ef971a0cfe4dcc90d7da0ece51492cacf92
parent8dc105079d3242a0352c726994cbedd172111111 (diff)
downloadOpenPlatformPkg-8e01088dfe0ce65d00d1488b6ee08390b3a3bb1a.tar.gz
Import APM XGene platform
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
-rw-r--r--Platforms/APM/XGene/APMXGene-Mustang-GFC.dsc467
-rw-r--r--Platforms/APM/XGene/APMXGene-Mustang-GFC.fdf407
-rw-r--r--Platforms/APM/XGene/APMXGene-Mustang-UHP.dsc467
-rw-r--r--Platforms/APM/XGene/APMXGene-Mustang.dsc462
-rw-r--r--Platforms/APM/XGene/APMXGene-Mustang.fdf402
-rw-r--r--Platforms/APM/XGene/APMXGene.dec208
-rw-r--r--Platforms/APM/XGene/APMXGene.dsc.inc329
-rw-r--r--Platforms/APM/XGene/AcpiPlatformDxe/AcpiPlatform.c84
-rw-r--r--Platforms/APM/XGene/AcpiPlatformDxe/AcpiPlatformDxe.inf78
-rwxr-xr-xPlatforms/APM/XGene/AcpiPlatformDxe/XGeneCPU.c202
-rwxr-xr-xPlatforms/APM/XGene/AcpiPlatformDxe/XGeneCPU.h22
-rwxr-xr-xPlatforms/APM/XGene/AcpiPlatformDxe/XGeneEthMAC.c512
-rwxr-xr-xPlatforms/APM/XGene/AcpiPlatformDxe/XGeneEthMAC.h21
-rw-r--r--Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/AcpiTables.inf37
-rw-r--r--Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Apic.asl190
-rw-r--r--Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Dbg2.asl74
-rw-r--r--Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Dsdt.asl3139
-rw-r--r--Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Facp.asl179
-rw-r--r--Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Facs.asl28
-rw-r--r--Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Gtdt.asl107
-rw-r--r--Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Mcfg.asl30
-rw-r--r--Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Rsdp.asl24
-rw-r--r--Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Spcr.asl46
-rw-r--r--Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Ssdt.asl21
-rw-r--r--Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Xsdt.asl29
-rwxr-xr-xPlatforms/APM/XGene/Applications/AppPkg.dec31
-rwxr-xr-xPlatforms/APM/XGene/Applications/AppPkg.dsc145
-rwxr-xr-xPlatforms/APM/XGene/Applications/UpgradeFirmware/Md5.c350
-rwxr-xr-xPlatforms/APM/XGene/Applications/UpgradeFirmware/Md5.h79
-rw-r--r--Platforms/APM/XGene/Applications/UpgradeFirmware/Slimpro.c183
-rw-r--r--Platforms/APM/XGene/Applications/UpgradeFirmware/Slimpro.h39
-rwxr-xr-xPlatforms/APM/XGene/Applications/UpgradeFirmware/UpgradeFirmware.c542
-rw-r--r--Platforms/APM/XGene/Applications/UpgradeFirmware/UpgradeFirmware.h66
-rwxr-xr-xPlatforms/APM/XGene/Applications/UpgradeFirmware/UpgradeFirmware.inf54
-rwxr-xr-xPlatforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/AhciMode.c2260
-rwxr-xr-xPlatforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/AhciMode.h381
-rwxr-xr-xPlatforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.c2134
-rwxr-xr-xPlatforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.h1152
-rwxr-xr-xPlatforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf67
-rwxr-xr-xPlatforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/ComponentName.c245
-rwxr-xr-xPlatforms/APM/XGene/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c1450
-rwxr-xr-xPlatforms/APM/XGene/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h519
-rwxr-xr-xPlatforms/APM/XGene/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf83
-rwxr-xr-xPlatforms/APM/XGene/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c2134
-rwxr-xr-xPlatforms/APM/XGene/Bus/Pci/PciHostBridgeDxe/XGenePcie.c653
-rwxr-xr-xPlatforms/APM/XGene/Bus/Pci/PciHostBridgeDxe/XGenePcie.h57
-rwxr-xr-xPlatforms/APM/XGene/Bus/Pci/PciHostBridgeDxe/XGenePcieCore.c644
-rwxr-xr-xPlatforms/APM/XGene/Bus/Pci/PciHostBridgeDxe/XGenePcieCore.h620
-rw-r--r--Platforms/APM/XGene/Bus/Usb/UsbControllerDxe/PciRootBridgeIo.c306
-rw-r--r--Platforms/APM/XGene/Bus/Usb/UsbControllerDxe/UsbController.c510
-rw-r--r--Platforms/APM/XGene/Bus/Usb/UsbControllerDxe/UsbController.h287
-rw-r--r--Platforms/APM/XGene/Bus/Usb/UsbControllerDxe/UsbControllerDxe.inf75
-rw-r--r--Platforms/APM/XGene/Bus/Usb/UsbControllerDxe/XGeneUsb.c379
-rw-r--r--Platforms/APM/XGene/DeviceTree/.gitignore3
-rw-r--r--Platforms/APM/XGene/DeviceTree/DeviceTree.inf43
-rw-r--r--Platforms/APM/XGene/DeviceTree/Setup.c216
-rw-r--r--Platforms/APM/XGene/DeviceTree/apm-mustang.dts45
-rw-r--r--Platforms/APM/XGene/DeviceTree/apm-storm.dtsi652
-rw-r--r--Platforms/APM/XGene/DeviceTree/dtb.format1
-rw-r--r--Platforms/APM/XGene/DeviceTree/header.c17
-rwxr-xr-xPlatforms/APM/XGene/DeviceTree/makedtb.sh3
-rw-r--r--Platforms/APM/XGene/DeviceTree/tail.c1
-rwxr-xr-xPlatforms/APM/XGene/Drivers/GpioDxe/Gpio.h129
-rwxr-xr-xPlatforms/APM/XGene/Drivers/GpioDxe/GpioDxe.c262
-rwxr-xr-xPlatforms/APM/XGene/Drivers/GpioDxe/GpioDxe.inf48
-rw-r--r--Platforms/APM/XGene/Drivers/L3CacheDxe/L3CacheDxe.inf55
-rw-r--r--Platforms/APM/XGene/Drivers/L3CacheDxe/XGeneL3c.c198
-rw-r--r--Platforms/APM/XGene/Drivers/L3CacheDxe/XGeneL3c.h87
-rw-r--r--Platforms/APM/XGene/Drivers/MciDxe/MciDxe.c1209
-rw-r--r--Platforms/APM/XGene/Drivers/MciDxe/MciDxe.h337
-rw-r--r--Platforms/APM/XGene/Drivers/MciDxe/MciDxe.inf57
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/ComponentName.c180
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/MT25408_PRM.h3408
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/Mellanox.c261
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/SnpDxe.c1436
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/SnpDxe.h367
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/SnpDxe.inf65
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/common.h325
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/hermon.c4316
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/hermon.h1206
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/ib_mad.h596
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/ib_packet.h154
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/ib_smc.c239
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/ib_smc.h25
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/infiniband.c1007
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/infiniband.h741
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/iobuf.h265
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/ipxe_ether.h47
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/ipxe_refcnt.h122
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/list.h471
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/mlx_bitops.h248
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/pcibackup.c86
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/pcibackup.h39
-rwxr-xr-xPlatforms/APM/XGene/Drivers/MellanoxDxe/tables.h526
-rw-r--r--Platforms/APM/XGene/Drivers/PCISataControllerDxe/ComponentName.c176
-rw-r--r--Platforms/APM/XGene/Drivers/PCISataControllerDxe/SataController.c1057
-rw-r--r--Platforms/APM/XGene/Drivers/PCISataControllerDxe/SataController.h542
-rw-r--r--Platforms/APM/XGene/Drivers/PCISataControllerDxe/SataControllerDxe.inf49
-rw-r--r--Platforms/APM/XGene/Drivers/STMicro/STMicro.c411
-rw-r--r--Platforms/APM/XGene/Drivers/STMicro/STMicro.inf41
-rwxr-xr-xPlatforms/APM/XGene/Drivers/SataControllerNewDxe/PciRootBridgeIo.c306
-rwxr-xr-xPlatforms/APM/XGene/Drivers/SataControllerNewDxe/SataController.c530
-rwxr-xr-xPlatforms/APM/XGene/Drivers/SataControllerNewDxe/SataController.h276
-rwxr-xr-xPlatforms/APM/XGene/Drivers/SataControllerNewDxe/SataControllerDxe.inf71
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/ComponentName.c180
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/SnpDxe.c1328
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/SnpDxe.h337
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/SnpDxe.inf94
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/classifier/apm_cle_access.c61
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/classifier/apm_cle_access.h163
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/classifier/apm_cle_csr.h20839
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/classifier/apm_cle_mgr.c610
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/classifier/apm_cle_mgr.h223
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/classifier/apm_preclass_api.c1159
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/classifier/apm_preclass_base.c315
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/classifier/apm_preclass_base.h90
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/classifier/apm_preclass_data.h728
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/ethernet/apm88xxxx_serdes_koolchip.h12349
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/ethernet/apm_cle_cfg.c150
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/ethernet/apm_enet.c833
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/ethernet/apm_enet_access.h271
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/ethernet/apm_enet_common.c658
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/ethernet/apm_enet_common.h789
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/ethernet/apm_enet_csr.h26426
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/ethernet/apm_enet_mac.c2496
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/ethernet/apm_enet_mac.h68
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/ethernet/apm_enet_misc.c1011
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/ethernet/apm_enet_misc.h48
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/ethernet/apm_xgenet_csr.h33267
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/ethernet/apm_xgenet_mac.c2902
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/ethernet/apm_xgenet_mac.h18
-rwxr-xr-xPlatforms/APM/XGene/Drivers/SnpDxe/mustang.h61
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/qm/xgene_qmtm.c932
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/qm/xgene_qmtm.h575
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/qm/xgene_qmtm_core.h248
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/qm/xgene_qmtm_csr.h173
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/qm/xgene_qmtm_main.c192
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/qm/xgene_qmtm_main.h149
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/qm/xgene_qmtm_msg.c147
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/qm/xgene_qmtm_shadowcat_csr.h21942
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/qm/xgene_qmtm_storm.c298
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/qm/xgene_qmtm_storm.h370
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/qm/xgene_qmtm_util.c212
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/qm/xgene_qmtm_util.h46
-rw-r--r--Platforms/APM/XGene/Drivers/SnpDxe/xgene_enet.c203
-rw-r--r--Platforms/APM/XGene/Include/APMXGeneAHBCCsr.h5024
-rw-r--r--Platforms/APM/XGene/Include/APMXGeneGFCCsr.h12640
-rwxr-xr-xPlatforms/APM/XGene/Include/APMXGeneGPIOCsr.h103
-rw-r--r--Platforms/APM/XGene/Include/APMXGeneMemc.h18
-rwxr-xr-xPlatforms/APM/XGene/Include/APMXGenePMD.h109
-rw-r--r--Platforms/APM/XGene/Include/APMXGeneSlimPROCSR.h13737
-rwxr-xr-xPlatforms/APM/XGene/Include/APMXGeneSocCsr.h158
-rw-r--r--Platforms/APM/XGene/Include/ArmPlatform.h28
-rw-r--r--Platforms/APM/XGene/Include/DWSPICsr.h76
-rw-r--r--Platforms/APM/XGene/Include/Library/DWSPI.h36
-rw-r--r--Platforms/APM/XGene/Include/Library/DeviceTree.h19
-rw-r--r--Platforms/APM/XGene/Include/Library/I2C.h132
-rw-r--r--Platforms/APM/XGene/Include/Library/SPI.h52
-rw-r--r--Platforms/APM/XGene/Include/Library/SPIFlash.h82
-rw-r--r--Platforms/APM/XGene/Include/Library/SlimproLib.h38
-rwxr-xr-xPlatforms/APM/XGene/Include/Library/SmbiosLib.h202
-rwxr-xr-xPlatforms/APM/XGene/Include/Library/XGenePHY.h23
-rw-r--r--Platforms/APM/XGene/Include/ipp_csr.h14401
-rw-r--r--Platforms/APM/XGene/Include/ipp_interface.h1486
-rw-r--r--Platforms/APM/XGene/Library/APMXGeneArmPlatformLib/APMXGeneArmPlatformHelper.S64
-rw-r--r--Platforms/APM/XGene/Library/APMXGeneArmPlatformLib/APMXGeneArmPlatformLib.c384
-rw-r--r--Platforms/APM/XGene/Library/APMXGeneArmPlatformLib/APMXGeneArmPlatformLib.inf65
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneArmPlatformLib/APMXGeneArmPlatformLibMemory.c136
-rw-r--r--Platforms/APM/XGene/Library/APMXGeneArmPlatformLib/APMXGeneClock.c115
-rw-r--r--Platforms/APM/XGene/Library/APMXGeneArmPlatformLib/APMXGeneClock.h31
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/APMXGeneMemc.c347
-rw-r--r--Platforms/APM/XGene/Library/APMXGeneMemcLib/APMXGeneMemcLib.inf61
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/ddr/apm_ddr.c952
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/ddr/apm_ddr_sdram.h608
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/ddr/ddr_addrmap.c715
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/ddr/ddr_config.c1124
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/ddr/ddr_fixed_configs.c452
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/ddr/ddr_lib.h415
-rw-r--r--Platforms/APM/XGene/Library/APMXGeneMemcLib/ddr/ddr_lrdimm_util.c1425
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/ddr/ddr_lrdimm_util.h34
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/ddr/ddr_main.c317
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/ddr/ddr_mcu.c944
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/ddr/ddr_mcu.h1606
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/ddr/ddr_phy.c1992
-rw-r--r--Platforms/APM/XGene/Library/APMXGeneMemcLib/ddr/ddr_phy_sw_training.c644
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/ddr/ddr_spd.c1009
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/ddr/ddr_spd.h202
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/ddr/ddr_util.c561
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/ddr/kc_phy_util_reg_flds.c38723
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/ddr/kc_phy_util_reg_flds.h3393
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGeneMemcLib/ddr/kc_phy_util_tasks.c348
-rw-r--r--Platforms/APM/XGene/Library/APMXGeneNorFlashPlatformLib/APMXGeneNorFlash.c353
-rw-r--r--Platforms/APM/XGene/Library/APMXGeneNorFlashPlatformLib/APMXGeneNorFlashPlatformLib.inf47
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGenePHYLib/APMXGenePHYLib.inf44
-rw-r--r--Platforms/APM/XGene/Library/APMXGenePHYLib/XGenePciePhyInit.c196
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGenePHYLib/XGeneSataPhyInit.c485
-rw-r--r--Platforms/APM/XGene/Library/APMXGenePHYLib/XGeneUsbPhyInit.c0
-rw-r--r--Platforms/APM/XGene/Library/APMXGenePHYLib/phy-xgene-pcie.c788
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGenePHYLib/phy-xgene-port.c52
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGenePHYLib/phy-xgene-port.h57
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGenePHYLib/phy-xgene-usb.c399
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGenePHYLib/phy-xgene.c2540
-rwxr-xr-xPlatforms/APM/XGene/Library/APMXGenePHYLib/phy-xgene.h86
-rw-r--r--Platforms/APM/XGene/Library/APMXGeneRTCLib/APMXGeneRealTimeClockLib.c530
-rw-r--r--Platforms/APM/XGene/Library/APMXGeneRTCLib/APMXGeneRealTimeClockLib.inf46
-rw-r--r--Platforms/APM/XGene/Library/APMXGeneRegDumpLib/APMXGeneRegDump.c61
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-rw-r--r--Platforms/APM/XGene/Library/DWSerialPortLib/DWSerialPortExtLib.c96
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-rwxr-xr-xPlatforms/APM/XGene/Library/DWSerialPortLib/DWUart.c271
-rwxr-xr-xPlatforms/APM/XGene/Library/DWSerialPortLib/DWUart.h98
-rw-r--r--Platforms/APM/XGene/Library/I2CLib/I2CLib.c646
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-rw-r--r--Platforms/APM/XGene/Library/ResetSystemLib/ResetSystemLib.c184
-rw-r--r--Platforms/APM/XGene/Library/ResetSystemLib/ResetSystemLib.inf41
-rw-r--r--Platforms/APM/XGene/Library/SPIFlashLib/SPIFlashLib.c187
-rw-r--r--Platforms/APM/XGene/Library/SPIFlashLib/SPIFlashLib.inf44
-rw-r--r--Platforms/APM/XGene/Library/SPILib/DWSPILib.c645
-rw-r--r--Platforms/APM/XGene/Library/SPILib/SPILib.inf54
-rw-r--r--Platforms/APM/XGene/Library/SlimproLib/SlimproLib.c320
-rw-r--r--Platforms/APM/XGene/Library/SlimproLib/SlimproLib.inf43
-rwxr-xr-xPlatforms/APM/XGene/Library/SmbiosLib/SmbiosLib.c354
-rwxr-xr-xPlatforms/APM/XGene/Library/SmbiosLib/SmbiosLib.inf46
-rw-r--r--Platforms/APM/XGene/MmcDxe/ComponentName.c162
-rw-r--r--Platforms/APM/XGene/MmcDxe/Diagnostics.c255
-rw-r--r--Platforms/APM/XGene/MmcDxe/Mmc.c454
-rw-r--r--Platforms/APM/XGene/MmcDxe/Mmc.h336
-rw-r--r--Platforms/APM/XGene/MmcDxe/MmcBlockIo.c653
-rw-r--r--Platforms/APM/XGene/MmcDxe/MmcDebug.c168
-rw-r--r--Platforms/APM/XGene/MmcDxe/MmcDxe.inf52
-rw-r--r--Platforms/APM/XGene/MmcDxe/MmcIdentification.c457
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c194
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf44
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/AArch64/CopyMem.c146
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/AArch64/CopyMemAlign.S60
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/AArch64/SetMem.c84
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/AArch64/SetMemAlign.S58
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.S171
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.asm173
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.S81
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm81
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf70
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/CompareMemWrapper.c66
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/CopyMem.c62
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/CopyMemWrapper.c72
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/MemLibGeneric.c265
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/MemLibGuid.c132
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/MemLibInternals.h252
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/ScanMem16Wrapper.c67
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/ScanMem32Wrapper.c66
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/ScanMem64Wrapper.c67
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/ScanMem8Wrapper.c99
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/SetMem.c53
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/SetMem16Wrapper.c64
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/SetMem32Wrapper.c64
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/SetMem64Wrapper.c64
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/SetMemWrapper.c95
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/ZeroMemWrapper.c52
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/DebugAgentSymbolsBaseLib/AArch64/DebugAgentException.S93
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/DebugAgentSymbolsBaseLib/Arm/DebugAgentException.S276
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/DebugAgentSymbolsBaseLib/Arm/DebugAgentException.asm273
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c350
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf47
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/DefaultExceptionHandlerLib/AArch64/DefaultExceptionHandler.c237
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/DefaultExceptionHandler.c268
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerBase.c35
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf45
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf42
-rw-r--r--Platforms/APM/XGene/Modules/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerUefi.c96
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Bds/Bds.c716
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Bds/Bds.inf80
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Bds/BdsHelper.c416
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Bds/BdsInternal.h286
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Bds/BootMenu.c946
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Bds/BootOption.c434
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Bds/BootOptionSupport.c959
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c129
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c1607
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.h425
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf72
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashFvbDxe.c931
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Include/Library/ArmPlatformLib.h173
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Include/Library/NorFlashPlatformLib.h57
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Library/EblCmdLib/AArch64/EblCmdMmu.c33
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Library/EblCmdLib/Arm/EblCmdMmu.c370
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Library/EblCmdLib/EblCmdFdt.c218
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.c456
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf66
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.c199
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf66
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.c161
-rw-r--r--Platforms/APM/XGene/Modules/ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf74
-rw-r--r--Platforms/APM/XGene/Modules/EmbeddedPkg/Include/Protocol/MmcHost.h170
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c2582
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.h369
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.c2593
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.h1300
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf71
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/ComponentName.c251
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/IdeMode.c2869
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/IdeMode.h204
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBus.c1916
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBus.h1101
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf74
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Ata/AtaBusDxe/AtaPassThruExecute.c1076
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Ata/AtaBusDxe/ComponentName.c238
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.c176
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.h152
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c409
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h412
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf119
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.c248
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.h238
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c1149
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.h289
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.c143
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.h86
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c2251
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.h519
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c2728
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h463
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.c394
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.h190
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c2048
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.h687
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c1648
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h165
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c731
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.h126
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.c88
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.h34
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c2273
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h463
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.c126
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.h55
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.c224
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.h146
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c758
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h213
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c2223
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h732
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf78
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c743
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-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c3682
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h1381
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Library/DxeNetLib/DxeNetLib.c3475
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf63
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Library/DxeNetLib/NetBuffer.c1892
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiSdt.c1114
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiSdt.h583
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTable.c90
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTable.h263
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf77
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c1828
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Acpi/AcpiTableDxe/Aml.c302
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AmlChild.c278
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AmlNamespace.c612
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AmlOption.c452
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AmlString.c545
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWrite.c834
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWrite.h711
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.c250
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf79
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.c728
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf84
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmmCommon.h80
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmmDxe.c562
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmmDxe.h202
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmmDxe.inf56
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/FaultTolerantWriteDxe/FtwMisc.c1342
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/FaultTolerantWriteDxe/UpdateWorkingBlock.c479
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c1166
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.h127
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf61
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Variable/RuntimeDxe/Reclaim.c170
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c3500
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.h521
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableDxe.c514
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf96
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.c965
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf98
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.c869
-rw-r--r--Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf69
-rw-r--r--Platforms/APM/XGene/Modules/MdePkg/Include/IndustryStandard/Acpi51.h2127
-rw-r--r--Platforms/APM/XGene/Modules/MdePkg/Include/IndustryStandard/Pci22.h829
-rw-r--r--Platforms/APM/XGene/Modules/MdePkg/Include/IndustryStandard/SmBios.h2275
-rw-r--r--Platforms/APM/XGene/Modules/MdePkg/Include/Protocol/FirmwareVolumeBlock.h388
-rwxr-xr-xPlatforms/APM/XGene/PlatformSmbiosDxe/PlatformSmbiosDxe.c132
-rwxr-xr-xPlatforms/APM/XGene/PlatformSmbiosDxe/PlatformSmbiosDxe.inf57
-rwxr-xr-xPlatforms/APM/XGene/PlatformSmbiosDxe/SmbiosTable.c448
-rw-r--r--Platforms/APM/XGene/Sec/Exception.S88
-rw-r--r--Platforms/APM/XGene/Sec/Helper.S179
-rw-r--r--Platforms/APM/XGene/Sec/Sec.c363
-rw-r--r--Platforms/APM/XGene/Sec/Sec.inf89
-rw-r--r--Platforms/APM/XGene/Sec/SecEntryPoint.S337
-rw-r--r--Platforms/APM/XGene/Sec/SecInternal.h77
-rw-r--r--Platforms/APM/XGene/Sec/SlimproBooting.c265
-rw-r--r--Platforms/APM/XGene/apm_changes.diff533
405 files changed, 386665 insertions, 0 deletions
diff --git a/Platforms/APM/XGene/APMXGene-Mustang-GFC.dsc b/Platforms/APM/XGene/APMXGene-Mustang-GFC.dsc
new file mode 100644
index 0000000..76e9f86
--- /dev/null
+++ b/Platforms/APM/XGene/APMXGene-Mustang-GFC.dsc
@@ -0,0 +1,467 @@
+##
+# Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# NOR Flash Layout
+#
+# 0x0000.0000 - 0x006F.FFFF => TianoCore
+# 0x0007.0000 - 0x0007.FFFF => TianoCore Variables
+#
+# 0x0080.0000 - 0x010F.FFFF => Linux Kernel
+# 0x0150.0000 - 0x0150.FFFF => DTS
+# 0x0160.0000 - 0x019F.FFFF => Init ram disk (uRamdisk)
+#
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = APMXGene-Mustang
+ PLATFORM_GUID = edcba8fd-a24e-489c-b4e9-93561f576500
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/APMXGene-Mustang
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = ArmPlatformPkg/APMXGenePkg/APMXGene-Mustang-GFC.fdf
+
+!include ArmPlatformPkg/APMXGenePkg/APMXGene.dsc.inc
+
+[LibraryClasses.common]
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
+ ArmPlatformLib|ArmPlatformPkg/APMXGenePkg/Library/APMXGeneArmPlatformLib/APMXGeneArmPlatformLib.inf
+ APMXGeneMemcLib|ArmPlatformPkg/APMXGenePkg/Library/APMXGeneMemcLib/APMXGeneMemcLib.inf
+ STMicroLib|ArmPlatformPkg/APMXGenePkg/Drivers/STMicro/STMicro.inf
+ I2CLib|ArmPlatformPkg/APMXGenePkg/Library/I2CLib/I2CLib.inf
+ SPILib|ArmPlatformPkg/APMXGenePkg/Library/SPILib/SPILib.inf
+ SPIFlashLib|ArmPlatformPkg/APMXGenePkg/Library/SPIFlashLib/SPIFlashLib.inf
+ SerialPortLib|ArmPlatformPkg/APMXGenePkg/Library/DWSerialPortLib/DWSerialPortLib.inf
+ RegDumpLib|ArmPlatformPkg/APMXGenePkg/Library/APMXGeneRegDumpLib/APMXGeneRegDump.inf
+ ArmPlatformDeviceTree|ArmPlatformPkg/APMXGenePkg/DeviceTree/DeviceTree.inf
+
+ # ARM General Interrupt Driver in Secure and Non-secure
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+
+ # Network General
+ NetLib|ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+ XGenePHYLib|ArmPlatformPkg/APMXGenePkg/Library/APMXGenePHYLib/APMXGenePHYLib.inf
+
+[LibraryClasses.common.SEC]
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf
+ ArmPlatformSecLib|ArmPlatformPkg/APMXGenePkg/Library/APMXGeneSecLib/APMXGeneSecLib.inf
+
+ #ArmGicSecLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+ #ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+
+[BuildOptions]
+ GCC:*_*_AARCH64_ARCHCC_FLAGS = -mgeneral-regs-only -DARM_CPU_AARCH64 -DAPM_XGENE -DAPM_XGENE_GFC_FLASH -DAARCH64_MP_PROTOCOL -fno-omit-frame-pointer
+ GCC:*_*_AARCH64_PP_FLAGS = -DARM_CPU_AARCH64
+ GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/APMXGenePkg/Include -I$(WORKSPACE)/ArmPlatformPkg/APMXGenePkg/Modules/ArmPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/APMXGenePkg/Modules/ArmPlatformPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/APMXGenePkg/Modules/EmbeddedPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/APMXGenePkg/Modules/MdePkg/Include
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ !ifdef $(EDK2_SKIP_PEICORE)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
+ gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
+ !endif
+
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+ # It could be set FALSE to save size.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+
+ #
+ # PCIE
+ #
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeResetGpio|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+[PcdsDynamicDefault.common]
+ gArmTokenSpaceGuid.PcdBootingLinuxUEFI|2
+
+[PcdsFixedAtBuild.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"1.1.0"
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"X-Gene Mustang Board"
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"Mustang"
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000
+
+ # Memory base start at 0x40.00000000 and above
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x4000000000
+ # System Memory (4GB)
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000
+
+
+ #
+ # NV Storage PCDs. Use base of 0x0780000 for NOR0
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x800000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x020000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x820000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x020000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x840000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x020000
+
+ gArmTokenSpaceGuid.PcdVFPEnabled|1
+
+ # Stacks for MPCores in Secure World (Top of OCM)
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x1D0FF000
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000
+ # For store Mem size after DDR calibration
+ gArmPlatformTokenSpaceGuid.PcdMemSizeAddr|0x1D0FEFF8
+
+ # For store TTB for initialize MMU before DDR calibration. 4K alignment
+ gArmPlatformTokenSpaceGuid.PcdTTBBaseAddr|0x1D0A6000
+
+ # Stacks for MPCores in Monitor Mode
+ #gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x2E008000
+ #gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100
+
+ # Stacks for MPCores in Normal World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x4001100000
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000
+
+ # Size of the region used by UEFI in permanent memory (Reserved 32MB)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000
+
+ #
+ # ARM Pcds
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000
+
+ # DW - Serial Terminal
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1C020000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|0
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+
+ #
+ # AHBC
+ gArmPlatformTokenSpaceGuid.PcdAHBCRegisterBase|0x1f2a0000
+
+ # DW SPI
+ gArmPlatformTokenSpaceGuid.PcdDWSpiBaseAddress|0x1C025000
+ gArmPlatformTokenSpaceGuid.PcdDWSpiClkInHz|12000000
+ gArmPlatformTokenSpaceGuid.PcdDWSpiMaxCS|3
+ gArmPlatformTokenSpaceGuid.PcdDWSpiFifoDepth|256
+ gArmPlatformTokenSpaceGuid.PcdDWSpiSysClk|100000000
+ gArmPlatformTokenSpaceGuid.PcdDWSpiVerId|0x3331352A
+
+ # DW I2C
+ gArmPlatformTokenSpaceGuid.PcdSysClkInHz|100000000
+
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x78090000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x780a0000
+
+ #
+ # ARM OS Loader
+ #
+ # Note that MemoryMapped when boot from SPI NOR must be PcdSystemMemoryBase + PcdSPIFlashMappedBaseOffset + (Offset in Flash. This offset must above 0x800000).
+ gArmTokenSpaceGuid.PcdArmMachineType|2272
+
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"BOOT OS LOADER"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyS0,115200 root=/dev/ram rw earlyprintk=uart8250-32bit,0x1c020000 debug"
+
+ # From NOR MTD
+ #gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(F40A3869-92C4-4275-8501-4491A1A20C19)/\\uImage"
+ #gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(F40A3869-92C4-4275-8501-4491A1A20C19)/\\apm-mustang.dtb"
+ #gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(F40A3869-92C4-4275-8501-4491A1A20C19)/\\uRamdisk"
+
+ # From SD
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(B225ED30-6DFD-43A9-BF6B-5753358F2F70)/HD(1,MBR,0x00000000,0x800,0x3AE800)/efi\\boot\\bootaa64.efi"
+ gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(B225ED30-6DFD-43A9-BF6B-5753358F2F70)/HD(1,MBR,0x00000000,0x800,0x1D7400)/\\apm-mustang.dtb"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(B225ED30-6DFD-43A9-BF6B-5753358F2F70)/HD(1,MBR,0x00000000,0x800,0x1D7400)/\\uRamdisk"
+
+ # From U-Boot Memory (All images)
+ # This helps speed up Tianocore and UEFI/Linux testing
+ # Mustang=> tftp 0x4002000000 ${user_dir}/mustang_tianocore_ubt.fd
+ # Mustang=> tftp 0x1d000000 ${user_dir}/mustang_tianocore_sec_ubt.fd
+ # Mustang=> tftp 0x4004800000 ${user_dir}/uImage
+ # Mustang=> tftp 0x4005500000 ${user_dir}/mustang.dtb
+ # Mustang=> tftp 0x4005600000 ${user_dir}/uRamdisk
+ # Mustang=> go 0x1d000000
+ # Note, You need to erase Tianocore old "Boot Menu configration" if
+ # you are going "From NOR MTD" to "U-Boot Memory (All images)."
+ # If this is the case, do the following from U-Boot.
+ # Mustang=> sf probe 0; sf erase 0x700000 0x100000
+ #gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(02118005-9DA7-443A-92D5-781F022AEDBB)/MemoryMapped(0x0,0x4004800000,0x40054FFFFF)"
+ #gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(02118005-9DA7-443A-92D5-781F022AEDBB)/MemoryMapped(0x0,0x4005500000,0x40550FFFF)"
+ #gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(02118005-9DA7-443A-92D5-781F022AEDBB)/MemoryMapped(0x0,0x4005600000,0x40087FFFFF)"
+
+ #Map SPI_NOR flash from 0x800000 to 0x800000 + PcdSPIFlashMappedLen to PcdSystemMemoryBase + PcdSPIFlashMappedBaseOffset + 0x800000. Need to fix it for fast booting
+ #gArmPlatformTokenSpaceGuid.PcdSPIFlashMappedBaseOffset|0x4000000
+ #gArmPlatformTokenSpaceGuid.PcdSPIFlashMappedLen|0x1000000
+
+ # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+ gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|5
+
+ #
+ # ARM Architectual Timer Frequency
+ #
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000
+
+ # SATA
+ gArmPlatformTokenSpaceGuid.PcdSataControllerMask|0x6 # Controller 1,2
+
+ # USB
+ gArmPlatformTokenSpaceGuid.PcdUsbControllerMask|0x3
+
+ #
+ # SD
+ #
+ gArmPlatformTokenSpaceGuid.PcdSDIOCapLow|0xA0FC1970
+ gArmPlatformTokenSpaceGuid.PcdSDIOCapHigh|0x0000008F
+ gArmPlatformTokenSpaceGuid.PcdSDIOHostPhyEnableMask|1
+
+ #
+ # PCIE
+ #
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeMask|0x1 # Port 0 enabled
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeGen|0x33333
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeWidth|0x48148
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeResetGpioPin|0x19
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+ #
+ # SEC
+ #
+ # ArmPlatformPkg/Sec/Sec.inf
+ ArmPlatformPkg/APMXGenePkg/Sec/Sec.inf {
+ <LibraryClasses>
+ ArmPlatformSecLib|ArmPlatformPkg/APMXGenePkg/Library/APMXGeneSecLib/APMXGeneSecLib.inf
+ APMXGeneMemcLib|ArmPlatformPkg/APMXGenePkg/Library/APMXGeneMemcLib/APMXGeneMemcLib.inf
+ }
+
+ #
+ # PEI Phase modules
+ #
+ !ifdef $(EDK2_SKIP_PEICORE)
+ ArmPlatformPkg/PrePi/PeiMPCore.inf {
+ <LibraryClasses>
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
+ ArmPlatformLib|ArmPlatformPkg/APMXGenePkg/Library/APMXGeneArmPlatformLib/APMXGeneArmPlatformLib.inf
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf
+ }
+ !else
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf {
+ <LibraryClasses>
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf
+ }
+ MdeModulePkg/Core/Pei/PeiMain.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ ArmPlatformPkg/APMXGenePkg/Modules/ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ }
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ Nt32Pkg/BootModePei/BootModePei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+ !endif
+
+ #
+ # DXE
+ #
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+
+ #
+ # SMBIOS
+ #
+ ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ ArmPlatformPkg/APMXGenePkg/PlatformSmbiosDxe/PlatformSmbiosDxe.inf {
+ <LibraryClasses>
+ SmbiosLib|ArmPlatformPkg/APMXGenePkg/Library/SmbiosLib/SmbiosLib.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Modules/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ #MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ #MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ EmbeddedPkg/SerialDxe/SerialDxe.inf
+
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ #MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ #ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ #
+ # Multimedia Card Interface
+ #
+ ArmPlatformPkg/APMXGenePkg/MmcDxe/MmcDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Drivers/MciDxe/MciDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # USB XHCI Support
+ #
+ ArmPlatformPkg/APMXGenePkg/Bus/Usb/UsbControllerDxe/UsbControllerDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+ #
+ # Application
+ #
+ EmbeddedPkg/Ebl/Ebl.inf
+
+ !ifdef $(EDK2_ARMVE_UEFI2_SHELL)
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ FileHandleLib|ShellPkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ SortLib|ShellPkg/Library/UefiSortLib/UefiSortLib.inf
+ PathLib|MdeModulePkg/Library/BasePathLib/BasePathLib.inf
+
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000
+ }
+ !endif
+
+ #
+ # ACPI Support
+ #
+ ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ ArmPlatformPkg/APMXGenePkg/AcpiPlatformDxe/AcpiPlatformDxe.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ }
+ ArmPlatformPkg/APMXGenePkg/AcpiTables/APMXGene-Mustang/AcpiTables.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Modules/ArmPlatformPkg/Bds/Bds.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ }
+
+ #
+ # Network stack drivers
+ #
+ MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Drivers/SnpDxe/SnpDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Drivers/MellanoxDxe/SnpDxe.inf
+
+ #
+ # PCI Support
+ #
+ ArmPlatformPkg/APMXGenePkg/Drivers/GpioDxe/GpioDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ }
+ ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
+ # IDE/AHCI Support
+ #
+ ArmPlatformPkg/APMXGenePkg/Drivers/SataControllerNewDxe/SataControllerDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Drivers/PCISataControllerDxe/SataControllerDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+ #
+ # Misc
+ #
+ ArmPlatformPkg/APMXGenePkg/Drivers/L3CacheDxe/L3CacheDxe.inf
diff --git a/Platforms/APM/XGene/APMXGene-Mustang-GFC.fdf b/Platforms/APM/XGene/APMXGene-Mustang-GFC.fdf
new file mode 100644
index 0000000..c65cdf2
--- /dev/null
+++ b/Platforms/APM/XGene/APMXGene-Mustang-GFC.fdf
@@ -0,0 +1,407 @@
+##
+# Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+[FD.Sec_APMXGene-Mustang]
+BaseAddress = 0x8100000000|gArmTokenSpaceGuid.PcdSecureFdBaseAddress #The base address of the Secure FLASH Device.
+Size = 0x00040000|gArmTokenSpaceGuid.PcdSecureFdSize #The size in bytes of the Secure FLASH Device
+ErasePolarity = 1
+BlockSize = 0x00001000
+NumBlocks = 0x40
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00040000
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
+FV = FVMAIN_SEC
+
+[FD.APMXGene-Mustang]
+BaseAddress = 0x8100040000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x1c0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00001000
+NumBlocks = 0x1c0
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x0|0x1c0000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FVMAIN_SEC]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/APMXGenePkg/Sec/Sec.inf
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 16 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF ArmPlatformPkg/APMXGenePkg/Modules/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ #INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ #INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF EmbeddedPkg/SerialDxe/SerialDxe.inf
+
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ #INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ #
+ # ACPI Table
+ INF ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF ArmPlatformPkg/APMXGenePkg/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF RuleOverride=ACPITABLE ArmPlatformPkg/APMXGenePkg/AcpiTables/APMXGene-Mustang/AcpiTables.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatBinPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # USB XHCI Support
+ #
+ INF ArmPlatformPkg/APMXGenePkg/Bus/Usb/UsbControllerDxe/UsbControllerDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+ #
+ # Multimedia Card Interface
+ #
+ INF ArmPlatformPkg/APMXGenePkg/MmcDxe/MmcDxe.inf
+ INF ArmPlatformPkg/APMXGenePkg/Drivers/MciDxe/MciDxe.inf
+
+ #
+ # Network stack drivers
+ #
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF ArmPlatformPkg/APMXGenePkg/Drivers/SnpDxe/SnpDxe.inf
+ INF ArmPlatformPkg/APMXGenePkg/Drivers/MellanoxDxe/SnpDxe.inf
+
+ #
+ # PCI Support
+ #
+ INF ArmPlatformPkg/APMXGenePkg/Drivers/GpioDxe/GpioDxe.inf
+ INF ArmPlatformPkg/APMXGenePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ INF ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+
+ #
+ # IDE/AHCI Support
+ #
+ INF ArmPlatformPkg/APMXGenePkg/Drivers/SataControllerNewDxe/SataControllerDxe.inf
+ INF ArmPlatformPkg/APMXGenePkg/Drivers/PCISataControllerDxe/SataControllerDxe.inf
+ INF ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF EmbeddedPkg/Ebl/Ebl.inf
+
+!if $(EDK2_ARMVE_UEFI2_SHELL) == 1
+ INF ShellPkg/Application/Shell/Shell.inf
+!endif
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF ArmPlatformPkg/APMXGenePkg/Modules/ArmPlatformPkg/Bds/Bds.inf
+
+ #
+ # Smbios
+ #
+ INF ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ INF ArmPlatformPkg/APMXGenePkg/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+ #
+ # Misc
+ #
+ INF ArmPlatformPkg/APMXGenePkg/Drivers/L3CacheDxe/L3CacheDxe.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+!if $(EDK2_SKIP_PEICORE) == 1
+ INF ArmPlatformPkg/PrePi/PeiMPCore.inf
+!else
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF ArmPlatformPkg/APMXGenePkg/Modules/ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+!endif
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 128 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ASL |.aml
+ }
diff --git a/Platforms/APM/XGene/APMXGene-Mustang-UHP.dsc b/Platforms/APM/XGene/APMXGene-Mustang-UHP.dsc
new file mode 100644
index 0000000..610c00f
--- /dev/null
+++ b/Platforms/APM/XGene/APMXGene-Mustang-UHP.dsc
@@ -0,0 +1,467 @@
+##
+# Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# NOR Flash Layout
+#
+# 0x0000.0000 - 0x006F.FFFF => TianoCore
+# 0x0007.0000 - 0x0007.FFFF => TianoCore Variables
+#
+# 0x0080.0000 - 0x010F.FFFF => Linux Kernel
+# 0x0150.0000 - 0x0150.FFFF => DTS
+# 0x0160.0000 - 0x019F.FFFF => Init ram disk (uRamdisk)
+#
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = APMXGene-Mustang
+ PLATFORM_GUID = edcba8fd-a24e-489c-b4e9-93561f576500
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/APMXGene-Mustang
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = ArmPlatformPkg/APMXGenePkg/APMXGene-Mustang.fdf
+
+!include ArmPlatformPkg/APMXGenePkg/APMXGene.dsc.inc
+
+[LibraryClasses.common]
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
+ ArmPlatformLib|ArmPlatformPkg/APMXGenePkg/Library/APMXGeneArmPlatformLib/APMXGeneArmPlatformLib.inf
+ APMXGeneMemcLib|ArmPlatformPkg/APMXGenePkg/Library/APMXGeneMemcLib/APMXGeneMemcLib.inf
+ STMicroLib|ArmPlatformPkg/APMXGenePkg/Drivers/STMicro/STMicro.inf
+ I2CLib|ArmPlatformPkg/APMXGenePkg/Library/I2CLib/I2CLib.inf
+ SPILib|ArmPlatformPkg/APMXGenePkg/Library/SPILib/SPILib.inf
+ SPIFlashLib|ArmPlatformPkg/APMXGenePkg/Library/SPIFlashLib/SPIFlashLib.inf
+ SerialPortLib|ArmPlatformPkg/APMXGenePkg/Library/DWSerialPortLib/DWSerialPortLib.inf
+ RegDumpLib|ArmPlatformPkg/APMXGenePkg/Library/APMXGeneRegDumpLib/APMXGeneRegDump.inf
+ ArmPlatformDeviceTree|ArmPlatformPkg/APMXGenePkg/DeviceTree/DeviceTree.inf
+
+ # ARM General Interrupt Driver in Secure and Non-secure
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+
+ # Network General
+ NetLib|ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+ XGenePHYLib|ArmPlatformPkg/APMXGenePkg/Library/APMXGenePHYLib/APMXGenePHYLib.inf
+
+[LibraryClasses.common.SEC]
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf
+ ArmPlatformSecLib|ArmPlatformPkg/APMXGenePkg/Library/APMXGeneSecLib/APMXGeneSecLib.inf
+
+ #ArmGicSecLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+ #ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+
+[BuildOptions]
+ GCC:*_*_AARCH64_ARCHCC_FLAGS = -mgeneral-regs-only -DARM_CPU_AARCH64 -DAPM_XGENE -DAPM_XGENE_SPI_FLASH -DAPM_XGENE_UHP -DAARCH64_MP_PROTOCOL -fno-omit-frame-pointer
+ GCC:*_*_AARCH64_PP_FLAGS = -DARM_CPU_AARCH64
+ GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/APMXGenePkg/Include -I$(WORKSPACE)/ArmPlatformPkg/APMXGenePkg/Modules/ArmPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/APMXGenePkg/Modules/ArmPlatformPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/APMXGenePkg/Modules/EmbeddedPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/APMXGenePkg/Modules/MdePkg/Include
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ !ifdef $(EDK2_SKIP_PEICORE)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
+ gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
+ !endif
+
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+ # It could be set FALSE to save size.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+
+ #
+ # PCIE
+ #
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeResetGpio|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+[PcdsDynamicDefault.common]
+ gArmTokenSpaceGuid.PcdBootingLinuxUEFI|2
+
+[PcdsFixedAtBuild.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"1.1.0"
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"X-Gene Mustang Board"
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"Mustang"
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000
+
+ # Memory base start at 0x40.00000000 and above
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x4000000000
+ # System Memory (4GB)
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000
+
+
+ #
+ # NV Storage PCDs. Use base of 0x0780000 for NOR0
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x800000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x020000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x820000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x020000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x840000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x020000
+
+ gArmTokenSpaceGuid.PcdVFPEnabled|1
+
+ # Stacks for MPCores in Secure World (Top of OCM)
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x1D0FF000
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000
+ # For store Mem size after DDR calibration
+ gArmPlatformTokenSpaceGuid.PcdMemSizeAddr|0x1D0FEFF8
+
+ # For store TTB for initialize MMU before DDR calibration. 4K alignment
+ gArmPlatformTokenSpaceGuid.PcdTTBBaseAddr|0x1D0A6000
+
+ # Stacks for MPCores in Monitor Mode
+ #gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x2E008000
+ #gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100
+
+ # Stacks for MPCores in Normal World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x4001100000
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000
+
+ # Size of the region used by UEFI in permanent memory (Reserved 32MB)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000
+
+ #
+ # ARM Pcds
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000
+
+ # DW - Serial Terminal
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1C020000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|0
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+
+ #
+ # AHBC
+ gArmPlatformTokenSpaceGuid.PcdAHBCRegisterBase|0x1f2a0000
+
+ # DW SPI
+ gArmPlatformTokenSpaceGuid.PcdDWSpiBaseAddress|0x1C025000
+ gArmPlatformTokenSpaceGuid.PcdDWSpiClkInHz|12000000
+ gArmPlatformTokenSpaceGuid.PcdDWSpiMaxCS|3
+ gArmPlatformTokenSpaceGuid.PcdDWSpiFifoDepth|256
+ gArmPlatformTokenSpaceGuid.PcdDWSpiSysClk|100000000
+ gArmPlatformTokenSpaceGuid.PcdDWSpiVerId|0x3331352A
+
+ # DW I2C
+ gArmPlatformTokenSpaceGuid.PcdSysClkInHz|100000000
+
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x78090000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x780a0000
+
+ #
+ # ARM OS Loader
+ #
+ # Note that MemoryMapped when boot from SPI NOR must be PcdSystemMemoryBase + PcdSPIFlashMappedBaseOffset + (Offset in Flash. This offset must above 0x800000).
+ gArmTokenSpaceGuid.PcdArmMachineType|2272
+
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"BOOT OS LOADER"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyS0,115200 root=/dev/ram rw earlyprintk=uart8250-32bit,0x1c020000 debug"
+
+ # From NOR MTD
+ #gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(F40A3869-92C4-4275-8501-4491A1A20C19)/\\uImage"
+ #gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(F40A3869-92C4-4275-8501-4491A1A20C19)/\\apm-mustang.dtb"
+ #gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(F40A3869-92C4-4275-8501-4491A1A20C19)/\\uRamdisk"
+
+ # From SD
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(B225ED30-6DFD-43A9-BF6B-5753358F2F70)/HD(1,MBR,0x00000000,0x800,0x3AE800)/efi\\boot\\bootaa64.efi"
+ gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(B225ED30-6DFD-43A9-BF6B-5753358F2F70)/HD(1,MBR,0x00000000,0x800,0x1D7400)/\\apm-mustang.dtb"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(B225ED30-6DFD-43A9-BF6B-5753358F2F70)/HD(1,MBR,0x00000000,0x800,0x1D7400)/\\uRamdisk"
+
+ # From U-Boot Memory (All images)
+ # This helps speed up Tianocore and UEFI/Linux testing
+ # Mustang=> tftp 0x4002000000 ${user_dir}/mustang_tianocore_ubt.fd
+ # Mustang=> tftp 0x1d000000 ${user_dir}/mustang_tianocore_sec_ubt.fd
+ # Mustang=> tftp 0x4004800000 ${user_dir}/uImage
+ # Mustang=> tftp 0x4005500000 ${user_dir}/mustang.dtb
+ # Mustang=> tftp 0x4005600000 ${user_dir}/uRamdisk
+ # Mustang=> go 0x1d000000
+ # Note, You need to erase Tianocore old "Boot Menu configration" if
+ # you are going "From NOR MTD" to "U-Boot Memory (All images)."
+ # If this is the case, do the following from U-Boot.
+ # Mustang=> sf probe 0; sf erase 0x700000 0x100000
+ #gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(02118005-9DA7-443A-92D5-781F022AEDBB)/MemoryMapped(0x0,0x4004800000,0x40054FFFFF)"
+ #gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(02118005-9DA7-443A-92D5-781F022AEDBB)/MemoryMapped(0x0,0x4005500000,0x40550FFFF)"
+ #gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(02118005-9DA7-443A-92D5-781F022AEDBB)/MemoryMapped(0x0,0x4005600000,0x40087FFFFF)"
+
+ #Map SPI_NOR flash from 0x800000 to 0x800000 + PcdSPIFlashMappedLen to PcdSystemMemoryBase + PcdSPIFlashMappedBaseOffset + 0x800000. Need to fix it for fast booting
+ #gArmPlatformTokenSpaceGuid.PcdSPIFlashMappedBaseOffset|0x4000000
+ #gArmPlatformTokenSpaceGuid.PcdSPIFlashMappedLen|0x1000000
+
+ # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+ gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|5
+
+ #
+ # ARM Architectual Timer Frequency
+ #
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000
+
+ # SATA
+ gArmPlatformTokenSpaceGuid.PcdSataControllerMask|0x6 # Controller 1,2
+
+ # USB
+ gArmPlatformTokenSpaceGuid.PcdUsbControllerMask|0x3
+
+ #
+ # SD
+ #
+ gArmPlatformTokenSpaceGuid.PcdSDIOCapLow|0xA0FC1970
+ gArmPlatformTokenSpaceGuid.PcdSDIOCapHigh|0x0000008F
+ gArmPlatformTokenSpaceGuid.PcdSDIOHostPhyEnableMask|1
+
+ #
+ # PCIE
+ #
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeMask|0x1 # Port 0 enabled
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeGen|0x33333
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeWidth|0x48148
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeResetGpioPin|0x19
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+ #
+ # SEC
+ #
+ # ArmPlatformPkg/Sec/Sec.inf
+ ArmPlatformPkg/APMXGenePkg/Sec/Sec.inf {
+ <LibraryClasses>
+ ArmPlatformSecLib|ArmPlatformPkg/APMXGenePkg/Library/APMXGeneSecLib/APMXGeneSecLib.inf
+ APMXGeneMemcLib|ArmPlatformPkg/APMXGenePkg/Library/APMXGeneMemcLib/APMXGeneMemcLib.inf
+ }
+
+ #
+ # PEI Phase modules
+ #
+ !ifdef $(EDK2_SKIP_PEICORE)
+ ArmPlatformPkg/PrePi/PeiMPCore.inf {
+ <LibraryClasses>
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
+ ArmPlatformLib|ArmPlatformPkg/APMXGenePkg/Library/APMXGeneArmPlatformLib/APMXGeneArmPlatformLib.inf
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf
+ }
+ !else
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf {
+ <LibraryClasses>
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf
+ }
+ MdeModulePkg/Core/Pei/PeiMain.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ ArmPlatformPkg/APMXGenePkg/Modules/ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ }
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ Nt32Pkg/BootModePei/BootModePei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+ !endif
+
+ #
+ # DXE
+ #
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+
+ #
+ # SMBIOS
+ #
+ ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ ArmPlatformPkg/APMXGenePkg/PlatformSmbiosDxe/PlatformSmbiosDxe.inf {
+ <LibraryClasses>
+ SmbiosLib|ArmPlatformPkg/APMXGenePkg/Library/SmbiosLib/SmbiosLib.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Modules/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ #MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ #MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ EmbeddedPkg/SerialDxe/SerialDxe.inf
+
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ #MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ #ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ #
+ # Multimedia Card Interface
+ #
+ ArmPlatformPkg/APMXGenePkg/MmcDxe/MmcDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Drivers/MciDxe/MciDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # USB XHCI Support
+ #
+ ArmPlatformPkg/APMXGenePkg/Bus/Usb/UsbControllerDxe/UsbControllerDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+ #
+ # Application
+ #
+ EmbeddedPkg/Ebl/Ebl.inf
+
+ !ifdef $(EDK2_ARMVE_UEFI2_SHELL)
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ FileHandleLib|ShellPkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ SortLib|ShellPkg/Library/UefiSortLib/UefiSortLib.inf
+ PathLib|MdeModulePkg/Library/BasePathLib/BasePathLib.inf
+
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000
+ }
+ !endif
+
+ #
+ # ACPI Support
+ #
+ ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ ArmPlatformPkg/APMXGenePkg/AcpiPlatformDxe/AcpiPlatformDxe.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ }
+ ArmPlatformPkg/APMXGenePkg/AcpiTables/APMXGene-Mustang/AcpiTables.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Modules/ArmPlatformPkg/Bds/Bds.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ }
+
+ #
+ # Network stack drivers
+ #
+ MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Drivers/SnpDxe/SnpDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Drivers/MellanoxDxe/SnpDxe.inf
+
+ #
+ # PCI Support
+ #
+ ArmPlatformPkg/APMXGenePkg/Drivers/GpioDxe/GpioDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ }
+ ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
+ # IDE/AHCI Support
+ #
+ ArmPlatformPkg/APMXGenePkg/Drivers/SataControllerNewDxe/SataControllerDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Drivers/PCISataControllerDxe/SataControllerDxe.inf
+ ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ ArmPlatformPkg/APMXGenePkg/Modules/MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+ #
+ # Misc
+ #
+ ArmPlatformPkg/APMXGenePkg/Drivers/L3CacheDxe/L3CacheDxe.inf
diff --git a/Platforms/APM/XGene/APMXGene-Mustang.dsc b/Platforms/APM/XGene/APMXGene-Mustang.dsc
new file mode 100644
index 0000000..1bace2b
--- /dev/null
+++ b/Platforms/APM/XGene/APMXGene-Mustang.dsc
@@ -0,0 +1,462 @@
+#
+# Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# NOR Flash Layout
+#
+# 0x0000.0000 - 0x006F.FFFF => TianoCore
+# 0x0007.0000 - 0x0007.FFFF => TianoCore Variables
+#
+# 0x0080.0000 - 0x010F.FFFF => Linux Kernel
+# 0x0150.0000 - 0x0150.FFFF => DTS
+# 0x0160.0000 - 0x019F.FFFF => Init ram disk (uRamdisk)
+#
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = APMXGene-Mustang
+ PLATFORM_GUID = edcba8fd-a24e-489c-b4e9-93561f576500
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/APMXGene-Mustang
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = OpenPlatformPkg/Platforms/APM/XGene/APMXGene-Mustang.fdf
+
+!include OpenPlatformPkg/Platforms/APM/XGene/APMXGene.dsc.inc
+
+[LibraryClasses.common]
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
+ ArmPlatformLib|OpenPlatformPkg/Platforms/APM/XGene/Library/APMXGeneArmPlatformLib/APMXGeneArmPlatformLib.inf
+ APMXGeneMemcLib|OpenPlatformPkg/Platforms/APM/XGene/Library/APMXGeneMemcLib/APMXGeneMemcLib.inf
+ STMicroLib|OpenPlatformPkg/Platforms/APM/XGene/Drivers/STMicro/STMicro.inf
+ I2CLib|OpenPlatformPkg/Platforms/APM/XGene/Library/I2CLib/I2CLib.inf
+ SPILib|OpenPlatformPkg/Platforms/APM/XGene/Library/SPILib/SPILib.inf
+ SPIFlashLib|OpenPlatformPkg/Platforms/APM/XGene/Library/SPIFlashLib/SPIFlashLib.inf
+ SerialPortLib|OpenPlatformPkg/Platforms/APM/XGene/Library/DWSerialPortLib/DWSerialPortLib.inf
+ RegDumpLib|OpenPlatformPkg/Platforms/APM/XGene/Library/APMXGeneRegDumpLib/APMXGeneRegDump.inf
+ ArmPlatformDeviceTree|OpenPlatformPkg/Platforms/APM/XGene/DeviceTree/DeviceTree.inf
+
+ # ARM General Interrupt Driver in Secure and Non-secure
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+
+ # Network General
+ NetLib|OpenPlatformPkg/Platforms/APM/XGene/Modules/MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+ XGenePHYLib|OpenPlatformPkg/Platforms/APM/XGene/Library/APMXGenePHYLib/APMXGenePHYLib.inf
+
+[LibraryClasses.common.SEC]
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf
+ ArmPlatformSecLib|OpenPlatformPkg/Platforms/APM/XGene/Library/APMXGeneSecLib/APMXGeneSecLib.inf
+
+ #ArmGicSecLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+ #ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+
+[BuildOptions]
+ GCC:*_*_AARCH64_ARCHCC_FLAGS = -mgeneral-regs-only -DARM_CPU_AARCH64 -DAPM_XGENE -DAPM_XGENE_SPI_FLASH -DAPM_XGENE_BOOT_SPI_NOR -DAARCH64_MP_PROTOCOL -fno-omit-frame-pointer
+ GCC:*_*_AARCH64_PP_FLAGS = -DARM_CPU_AARCH64
+ GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/OpenPlatformPkg/Platforms/APM/XGene/Include -I$(WORKSPACE)/OpenPlatformPkg/Platforms/APM/XGene/Modules/ArmPlatformPkg/Include -I$(WORKSPACE)/OpenPlatformPkg/Platforms/APM/XGene/Modules/EmbeddedPkg/Include -I$(WORKSPACE)/OpenPlatformPkg/Platforms/APM/XGene/Modules/MdePkg/Include
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ !ifdef $(EDK2_SKIP_PEICORE)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
+ gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
+ !endif
+
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+ # It could be set FALSE to save size.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+
+ #
+ # PCIE
+ #
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeResetGpio|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+[PcdsDynamicDefault.common]
+ gArmTokenSpaceGuid.PcdBootingLinuxUEFI|2
+
+[PcdsFixedAtBuild.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"1.1.0"
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"X-Gene Mustang Board"
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"Mustang"
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000
+
+ # Memory base start at 0x40.00000000 and above
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x4000000000
+ # System Memory (4GB)
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000
+
+
+ #
+ # NV Storage PCDs. Use base of 0x0780000 for NOR0
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x800000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x020000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x820000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x020000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x840000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x020000
+
+ gArmTokenSpaceGuid.PcdVFPEnabled|1
+
+ # Stacks for MPCores in Secure World (Top of OCM)
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x1D0FF000
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000
+ # For store Mem size after DDR calibration
+ gArmPlatformTokenSpaceGuid.PcdMemSizeAddr|0x1D0FEFF8
+
+ # For store TTB for initialize MMU before DDR calibration. 4K alignment
+ gArmPlatformTokenSpaceGuid.PcdTTBBaseAddr|0x1D0A6000
+
+ # Stacks for MPCores in Monitor Mode
+ #gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x2E008000
+ #gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100
+
+ # Stacks for MPCores in Normal World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x4001100000
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000
+
+ # Size of the region used by UEFI in permanent memory (Reserved 32MB)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000
+
+ #
+ # ARM Pcds
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000
+
+ # DW - Serial Terminal
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1C020000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|0
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+
+ #
+ # AHBC
+ gArmPlatformTokenSpaceGuid.PcdAHBCRegisterBase|0x1f2a0000
+
+ # DW SPI
+ gArmPlatformTokenSpaceGuid.PcdDWSpiBaseAddress|0x1C025000
+ gArmPlatformTokenSpaceGuid.PcdDWSpiClkInHz|12000000
+ gArmPlatformTokenSpaceGuid.PcdDWSpiMaxCS|3
+ gArmPlatformTokenSpaceGuid.PcdDWSpiFifoDepth|256
+ gArmPlatformTokenSpaceGuid.PcdDWSpiSysClk|100000000
+ gArmPlatformTokenSpaceGuid.PcdDWSpiVerId|0x3331352A
+
+ # DW I2C
+ gArmPlatformTokenSpaceGuid.PcdSysClkInHz|100000000
+
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x78090000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x780a0000
+
+ #
+ # ARM OS Loader
+ #
+ # Note that MemoryMapped when boot from SPI NOR must be PcdSystemMemoryBase + PcdSPIFlashMappedBaseOffset + (Offset in Flash. This offset must above 0x800000).
+ gArmTokenSpaceGuid.PcdArmMachineType|2272
+
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"BOOT OS LOADER"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyS0,115200 root=/dev/ram rw earlyprintk=uart8250-32bit,0x1c020000 debug"
+
+ # From NOR MTD
+ #gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(F40A3869-92C4-4275-8501-4491A1A20C19)/\\uImage"
+ #gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(F40A3869-92C4-4275-8501-4491A1A20C19)/\\apm-mustang.dtb"
+ #gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(F40A3869-92C4-4275-8501-4491A1A20C19)/\\uRamdisk"
+
+ # From SD
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(B225ED30-6DFD-43A9-BF6B-5753358F2F70)/HD(1,MBR,0x00000000,0x800,0x3AE800)/efi\\boot\\bootaa64.efi"
+ gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(B225ED30-6DFD-43A9-BF6B-5753358F2F70)/HD(1,MBR,0x00000000,0x800,0x1D7400)/\\apm-mustang.dtb"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(B225ED30-6DFD-43A9-BF6B-5753358F2F70)/HD(1,MBR,0x00000000,0x800,0x1D7400)/\\uRamdisk"
+
+ # From U-Boot Memory (All images)
+ # This helps speed up Tianocore and UEFI/Linux testing
+ # Mustang=> tftp 0x4002000000 ${user_dir}/mustang_tianocore_ubt.fd
+ # Mustang=> tftp 0x1d000000 ${user_dir}/mustang_tianocore_sec_ubt.fd
+ # Mustang=> tftp 0x4004800000 ${user_dir}/uImage
+ # Mustang=> tftp 0x4005500000 ${user_dir}/mustang.dtb
+ # Mustang=> tftp 0x4005600000 ${user_dir}/uRamdisk
+ # Mustang=> go 0x1d000000
+ # Note, You need to erase Tianocore old "Boot Menu configration" if
+ # you are going "From NOR MTD" to "U-Boot Memory (All images)."
+ # If this is the case, do the following from U-Boot.
+ # Mustang=> sf probe 0; sf erase 0x700000 0x100000
+ #gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(02118005-9DA7-443A-92D5-781F022AEDBB)/MemoryMapped(0x0,0x4004800000,0x40054FFFFF)"
+ #gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(02118005-9DA7-443A-92D5-781F022AEDBB)/MemoryMapped(0x0,0x4005500000,0x40550FFFF)"
+ #gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(02118005-9DA7-443A-92D5-781F022AEDBB)/MemoryMapped(0x0,0x4005600000,0x40087FFFFF)"
+
+ #Map SPI_NOR flash from 0x800000 to 0x800000 + PcdSPIFlashMappedLen to PcdSystemMemoryBase + PcdSPIFlashMappedBaseOffset + 0x800000. Need to fix it for fast booting
+ #gArmPlatformTokenSpaceGuid.PcdSPIFlashMappedBaseOffset|0x4000000
+ #gArmPlatformTokenSpaceGuid.PcdSPIFlashMappedLen|0x1000000
+
+ # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+ gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|5
+
+ #
+ # ARM Architectual Timer Frequency
+ #
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000
+
+ # SATA
+ gArmPlatformTokenSpaceGuid.PcdSataControllerMask|0x6 # Controller 1,2
+
+ # USB
+ gArmPlatformTokenSpaceGuid.PcdUsbControllerMask|0x3
+
+ #
+ # SD
+ #
+ gArmPlatformTokenSpaceGuid.PcdSDIOCapLow|0xA0FC1970
+ gArmPlatformTokenSpaceGuid.PcdSDIOCapHigh|0x0000008F
+ gArmPlatformTokenSpaceGuid.PcdSDIOHostPhyEnableMask|1
+
+ #
+ # PCIE
+ #
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeMask|0x1 # Port 0 enabled
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeGen|0x33333
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeWidth|0x48148
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeResetGpioPin|0x19
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+ #
+ # SEC
+ #
+ # ArmPlatformPkg/Sec/Sec.inf
+ OpenPlatformPkg/Platforms/APM/XGene/Sec/Sec.inf {
+ <LibraryClasses>
+ ArmPlatformSecLib|OpenPlatformPkg/Platforms/APM/XGene/Library/APMXGeneSecLib/APMXGeneSecLib.inf
+ APMXGeneMemcLib|OpenPlatformPkg/Platforms/APM/XGene/Library/APMXGeneMemcLib/APMXGeneMemcLib.inf
+ }
+
+ #
+ # PEI Phase modules
+ #
+ !ifdef $(EDK2_SKIP_PEICORE)
+ ArmPlatformPkg/PrePi/PeiMPCore.inf {
+ <LibraryClasses>
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
+ ArmPlatformLib|OpenPlatformPkg/Platforms/APM/XGene/Library/APMXGeneArmPlatformLib/APMXGeneArmPlatformLib.inf
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf
+ }
+ !else
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf {
+ <LibraryClasses>
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf
+ }
+ MdeModulePkg/Core/Pei/PeiMain.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ OpenPlatformPkg/Platforms/APM/XGene/Modules/ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ }
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ Nt32Pkg/BootModePei/BootModePei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+ !endif
+
+ #
+ # DXE
+ #
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+
+ #
+ # SMBIOS
+ #
+ OpenPlatformPkg/Platforms/APM/XGene/Modules/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ OpenPlatformPkg/Platforms/APM/XGene/PlatformSmbiosDxe/PlatformSmbiosDxe.inf {
+ <LibraryClasses>
+ SmbiosLib|OpenPlatformPkg/Platforms/APM/XGene/Library/SmbiosLib/SmbiosLib.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ OpenPlatformPkg/Platforms/APM/XGene/Modules/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ OpenPlatformPkg/Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ OpenPlatformPkg/Platforms/APM/XGene/Modules/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ #MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ #MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ EmbeddedPkg/SerialDxe/SerialDxe.inf
+
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ #MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ #ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ #
+ # Multimedia Card Interface
+ #
+ OpenPlatformPkg/Platforms/APM/XGene/MmcDxe/MmcDxe.inf
+ OpenPlatformPkg/Platforms/APM/XGene/Drivers/MciDxe/MciDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # USB XHCI Support
+ #
+ OpenPlatformPkg/Platforms/APM/XGene/Bus/Usb/UsbControllerDxe/UsbControllerDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ OpenPlatformPkg/Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+ !ifdef $(EDK2_ARMVE_UEFI2_SHELL)
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ FileHandleLib|ShellPkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ SortLib|ShellPkg/Library/UefiSortLib/UefiSortLib.inf
+ PathLib|MdeModulePkg/Library/BasePathLib/BasePathLib.inf
+
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000
+ }
+ !endif
+
+ #
+ # ACPI Support
+ #
+ OpenPlatformPkg/Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ OpenPlatformPkg/Platforms/APM/XGene/AcpiPlatformDxe/AcpiPlatformDxe.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ }
+ OpenPlatformPkg/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/AcpiTables.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ ArmPlatformPkg/Bds/Bds.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ }
+
+ #
+ # Network stack drivers
+ #
+ MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ OpenPlatformPkg/Platforms/APM/XGene/Drivers/SnpDxe/SnpDxe.inf
+ OpenPlatformPkg/Platforms/APM/XGene/Drivers/MellanoxDxe/SnpDxe.inf
+
+ #
+ # PCI Support
+ #
+ OpenPlatformPkg/Platforms/APM/XGene/Drivers/GpioDxe/GpioDxe.inf
+ OpenPlatformPkg/Platforms/APM/XGene/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ }
+ OpenPlatformPkg/Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
+ # IDE/AHCI Support
+ #
+ OpenPlatformPkg/Platforms/APM/XGene/Drivers/SataControllerNewDxe/SataControllerDxe.inf
+ OpenPlatformPkg/Platforms/APM/XGene/Drivers/PCISataControllerDxe/SataControllerDxe.inf
+ OpenPlatformPkg/Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ OpenPlatformPkg/Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+ #
+ # Misc
+ #
+ OpenPlatformPkg/Platforms/APM/XGene/Drivers/L3CacheDxe/L3CacheDxe.inf
diff --git a/Platforms/APM/XGene/APMXGene-Mustang.fdf b/Platforms/APM/XGene/APMXGene-Mustang.fdf
new file mode 100644
index 0000000..3ba3154
--- /dev/null
+++ b/Platforms/APM/XGene/APMXGene-Mustang.fdf
@@ -0,0 +1,402 @@
+##
+# Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+[FD.Sec_APMXGene-Mustang]
+BaseAddress = 0x1d000000|gArmTokenSpaceGuid.PcdSecureFdBaseAddress #The base address of the Secure FLASH Device.
+Size = 0x00040000|gArmTokenSpaceGuid.PcdSecureFdSize #The size in bytes of the Secure FLASH Device
+ErasePolarity = 1
+BlockSize = 0x00001000
+NumBlocks = 0x40
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00040000
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
+FV = FVMAIN_SEC
+
+[FD.APMXGene-Mustang]
+BaseAddress = 0x4002000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x1c0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00001000
+NumBlocks = 0x1c0
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x0|0x1c0000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FVMAIN_SEC]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF OpenPlatformPkg/Platforms/APM/XGene/Sec/Sec.inf
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 16 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF OpenPlatformPkg/Platforms/APM/XGene/Modules/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF OpenPlatformPkg/Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF OpenPlatformPkg/Platforms/APM/XGene/Modules/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ #INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ #INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF EmbeddedPkg/SerialDxe/SerialDxe.inf
+
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ #INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ #
+ # ACPI Table
+ INF OpenPlatformPkg/Platforms/APM/XGene/Modules/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF OpenPlatformPkg/Platforms/APM/XGene/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF RuleOverride=ACPITABLE OpenPlatformPkg/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/AcpiTables.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatBinPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # USB XHCI Support
+ #
+ INF OpenPlatformPkg/Platforms/APM/XGene/Bus/Usb/UsbControllerDxe/UsbControllerDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF OpenPlatformPkg/Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+ #
+ # Multimedia Card Interface
+ #
+ INF OpenPlatformPkg/Platforms/APM/XGene/MmcDxe/MmcDxe.inf
+ INF OpenPlatformPkg/Platforms/APM/XGene/Drivers/MciDxe/MciDxe.inf
+
+ #
+ # Network stack drivers
+ #
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF OpenPlatformPkg/Platforms/APM/XGene/Drivers/SnpDxe/SnpDxe.inf
+ INF OpenPlatformPkg/Platforms/APM/XGene/Drivers/MellanoxDxe/SnpDxe.inf
+
+ #
+ # PCI Support
+ #
+ INF OpenPlatformPkg/Platforms/APM/XGene/Drivers/GpioDxe/GpioDxe.inf
+ INF OpenPlatformPkg/Platforms/APM/XGene/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ INF OpenPlatformPkg/Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+
+ #
+ # IDE/AHCI Support
+ #
+ INF OpenPlatformPkg/Platforms/APM/XGene/Drivers/SataControllerNewDxe/SataControllerDxe.inf
+ INF OpenPlatformPkg/Platforms/APM/XGene/Drivers/PCISataControllerDxe/SataControllerDxe.inf
+ INF OpenPlatformPkg/Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF OpenPlatformPkg/Platforms/APM/XGene/Modules/MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+!if $(EDK2_ARMVE_UEFI2_SHELL) == 1
+ INF ShellPkg/Application/Shell/Shell.inf
+!endif
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF ArmPlatformPkg/Bds/Bds.inf
+
+ #
+ # Smbios
+ #
+ INF OpenPlatformPkg/Platforms/APM/XGene/Modules/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ INF OpenPlatformPkg/Platforms/APM/XGene/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+ #
+ # Misc
+ #
+ INF OpenPlatformPkg/Platforms/APM/XGene/Drivers/L3CacheDxe/L3CacheDxe.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+!if $(EDK2_SKIP_PEICORE) == 1
+ INF ArmPlatformPkg/PrePi/PeiMPCore.inf
+!else
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF OpenPlatformPkg/Platforms/APM/XGene/Modules/ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+!endif
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ASL |.aml
+ }
diff --git a/Platforms/APM/XGene/APMXGene.dec b/Platforms/APM/XGene/APMXGene.dec
new file mode 100644
index 0000000..7b97ff7
--- /dev/null
+++ b/Platforms/APM/XGene/APMXGene.dec
@@ -0,0 +1,208 @@
+##
+# Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = APMXGenePkg
+ PACKAGE_GUID = 84139d17-9469-44ca-980a-bff540e792b3
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
+[Guids.common]
+ gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
+ #
+ # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ #
+ gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }
+
+ ## Include/Guid/ArmGlobalVariableHob.h
+ gArmGlobalVariableGuid = { 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} }
+
+[Ppis]
+ ## Include/Ppi/ArmGlobalVariable.h
+ gArmGlobalVariablePpiGuid = { 0xab1c1816, 0xd542, 0x4e6f, {0x9b, 0x1e, 0x8e, 0xcd, 0x92, 0x53, 0xe2, 0xe7} }
+
+[PcdsFeatureFlag.common]
+ # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.
+ gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|TRUE|BOOLEAN|0x00000012
+
+ gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE|BOOLEAN|0x00000002
+ gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004
+
+ gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C
+ #PCIE
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeResetGpio|FALSE|BOOLEAN|0x00000076
+
+[PcdsFixedAtBuild.common]
+ # Stack for CPU Cores in Secure Mode (Top of OCM)
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x1D0FF000|UINT32|0x00000005
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000|UINT32|0x00000036
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006
+
+ # Stack for CPU Cores in Secure Monitor Mode
+ #gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
+ #gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008
+
+ # Stack for CPU Cores in Non Secure Mode
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x0|UINT64|0x00000009
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A
+
+ # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015
+
+ # Size to reserve in the primary core stack for PEI Global Variables
+ # = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */
+ gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016
+ # PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list
+ # PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped.
+ gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017
+ gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018
+
+ # Size to reserve in the primary core stack for SEC Global Variables
+ gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x0|UINT32|0x00000031
+
+ #
+ # XGene Peripherals
+ #
+
+ # DW UART
+ gArmPlatformTokenSpaceGuid.DWUartClkInHz|10000000|UINT32|0x0000001F
+ gArmPlatformTokenSpaceGuid.DWUartInteger|0|UINT32|0x00000020
+ gArmPlatformTokenSpaceGuid.DWUartFractional|0|UINT32|0x0000002D
+
+
+ # AHBC
+ gArmPlatformTokenSpaceGuid.PcdAHBCRegisterBase|0x1f2a0000|UINT64|0x0000003E
+
+ # SLimPro
+ gArmPlatformTokenSpaceGuid.PcdAPM88XXXXSlimproScuBase|0x17000000|UINT64|0x00000024
+
+ #
+ # BDS - Boot Manager
+ #
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L""|VOID*|0x0000000E
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""|VOID*|0x000000F
+ # PcdDefaultBootType define the type of the binary pointed by PcdDefaultBootDevicePath:
+ # - 0 = an EFI application
+ # - 1 = a Linux kernel with ATAG support
+ # - 2 = a Linux kernel with FDT support
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0|UINT32|0x00000010
+ gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L""|VOID*|0x00000011
+ gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x07000000|UINT32|0x00000020
+
+ ## Timeout value for displaying progressing bar in before boot OS.
+ # According to UEFI 2.0 spec, the default TimeOut should be 0xffff.
+ gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|0xffff|UINT16|0x0000001A
+
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C
+
+ # SDIO
+ gArmPlatformTokenSpaceGuid.PcdSDIOHostPhyEnableMask|0x00000001|UINT32|0x0000003D
+ gArmPlatformTokenSpaceGuid.PcdSDIORegisterBase|0x1C000000|UINT64|0x0000003F
+ gArmPlatformTokenSpaceGuid.PcdSDIOCapLow|0x0|UINT32|0x00000040
+ gArmPlatformTokenSpaceGuid.PcdSDIOCapHigh|0x0|UINT32|0x00000041
+
+ # DW SPI
+ gArmPlatformTokenSpaceGuid.PcdDWSpiClkInHz|4000000|UINT32|0x00000042
+ gArmPlatformTokenSpaceGuid.PcdDWSpiBaseAddress|0x1C025000|UINT64|0x00000043
+ gArmPlatformTokenSpaceGuid.PcdDWSpiMaxCS|3|UINT32|0x00000044
+ gArmPlatformTokenSpaceGuid.PcdDWSpiFifoDepth|256|UINT32|0x00000045
+ gArmPlatformTokenSpaceGuid.PcdDWSpiSysClk|100000000|UINT32|0x00000046
+ gArmPlatformTokenSpaceGuid.PcdDWSpiVerId|0x3331352A|UINT32|0x00000047
+
+ gArmPlatformTokenSpaceGuid.PcdSysClkInHz|100000000|UINT32|0x00000048
+
+ gArmPlatformTokenSpaceGuid.PcdSPIFlashBus|0x0|UINT32|0x00000049
+ gArmPlatformTokenSpaceGuid.PcdSPIFlashCS|0x0|UINT32|0x00000050
+ gArmPlatformTokenSpaceGuid.PcdSPIFlashMaxHz|4000000|UINT32|0x00000051
+
+ # AHCI common (Enable controller 2 and 3)
+ gArmPlatformTokenSpaceGuid.PcdSataControllerMask|0x1|UINT32|0x00000079
+
+ # AHCI Controller 3 (Enabled)
+ gArmPlatformTokenSpaceGuid.PcdAHCI3RegisterBase|0x1a800000|UINT64|0x00000055
+ gArmPlatformTokenSpaceGuid.PcdSata3SerdesRegisterBase|0x1f230000|UINT64|0x00000056
+ gArmPlatformTokenSpaceGuid.PcdSata3GenMax|3|UINT32|0x00000057
+ gArmPlatformTokenSpaceGuid.PcdSata3Irq|136|UINT32|0x00000058
+
+ # AHCI Controller 2 (Enabled)
+ gArmPlatformTokenSpaceGuid.PcdAHCI2RegisterBase|0x1a400000|UINT64|0x00000059
+ gArmPlatformTokenSpaceGuid.PcdSata2SerdesRegisterBase|0x1f220000|UINT64|0x0000005A
+ gArmPlatformTokenSpaceGuid.PcdSata2GenMax|3|UINT32|0x0000005B
+ gArmPlatformTokenSpaceGuid.PcdSata2Irq|135|UINT32|0x0000005C
+
+ # AHCI Controller 1 (disabled)
+ gArmPlatformTokenSpaceGuid.PcdAHCI1RegisterBase|0x1a000000|UINT64|0x0000005D
+ gArmPlatformTokenSpaceGuid.PcdSata1SerdesRegisterBase|0x1f210000|UINT64|0x0000005E
+ gArmPlatformTokenSpaceGuid.PcdSata1GenMax|3|UINT32|0x0000005F
+ gArmPlatformTokenSpaceGuid.PcdSata1Irq|134|UINT32|0x00000060
+
+ # XHCI common
+ gArmPlatformTokenSpaceGuid.PcdUsbControllerMask|0x0|UINT32|0x0000007D
+
+ # XHCI Controller 2
+ gArmPlatformTokenSpaceGuid.PcdXHCI2RegisterBase|0x19800000|UINT64|0x00000061
+ gArmPlatformTokenSpaceGuid.PcdUsb2CsrRegisterBase|0x1f290000|UINT64|0x00000062
+ gArmPlatformTokenSpaceGuid.PcdUsb2Irq|137|UINT32|0x00000063
+ gArmPlatformTokenSpaceGuid.PcdUsb2ClkSel|0|UINT32|0x00000064
+ gArmPlatformTokenSpaceGuid.PcdUsb2OvrcurEn|0|UINT32|0x00000065
+ gArmPlatformTokenSpaceGuid.PcdUsb2OvrcurIvrt|0|UINT32|0x00000066
+
+ # XHCI Controller 1
+ gArmPlatformTokenSpaceGuid.PcdXHCI1RegisterBase|0x19000000|UINT64|0x00000067
+ gArmPlatformTokenSpaceGuid.PcdUsb1CsrRegisterBase|0x1f280000|UINT64|0x00000068
+ gArmPlatformTokenSpaceGuid.PcdUsb1Irq|136|UINT32|0x00000069
+ gArmPlatformTokenSpaceGuid.PcdUsb1ClkSel|0|UINT32|0x0000006A
+ gArmPlatformTokenSpaceGuid.PcdUsb1OvrcurEn|0|UINT32|0x0000006B
+ gArmPlatformTokenSpaceGuid.PcdUsb1OvrcurIvrt|0|UINT32|0x0000006C
+
+ #PCIE
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeMask|0|UINT32|0x00000073
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeGen|0x33333|UINT32|0x00000074
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeWidth|0x48148|UINT32|0x00000075
+ gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeResetGpioPin|0x0|UINT64|0x00000077
+
+ # AHBC
+ gArmPlatformTokenSpaceGuid.PcdGPIORegisterBase|0x1c024000|UINT64|0x00000078
+
+ # Misc
+ gArmPlatformTokenSpaceGuid.PcdMemSizeAddr|0|UINT64|0x0000007A
+
+ gArmPlatformTokenSpaceGuid.PcdKernMailboxAddr|0|UINT64|0x0000007B
+ gArmPlatformTokenSpaceGuid.PcdTTBBaseAddr|0|UINT64|0x0000007C
+
+ ## APM RealTimeClock
+ gArmPlatformTokenSpaceGuid.PcdApmRtcBase|0x10510000|UINT64|0x0000007E
+
+ gArmPlatformTokenSpaceGuid.PcdL3cSize|8|UINT32|0x0000007F
+
+[PcdsDynamic.common]
+ gArmTokenSpaceGuid.PcdBootingLinuxUEFI|0|UINT32|0x00000080
+
diff --git a/Platforms/APM/XGene/APMXGene.dsc.inc b/Platforms/APM/XGene/APMXGene.dsc.inc
new file mode 100644
index 0000000..a7edc32
--- /dev/null
+++ b/Platforms/APM/XGene/APMXGene.dsc.inc
@@ -0,0 +1,329 @@
+##
+# Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[LibraryClasses.common]
+!if $(TARGET) == RELEASE
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+# UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
+!endif
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+ #
+ # Assume everything is fixed at build
+ #
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+ # 1/123 faster than Stm or Vstm version
+ #BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ BaseMemoryLib|OpenPlatformPkg/Platforms/APM/XGene/Modules/ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
+
+ # ARM Architectural Libraries
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ DefaultExceptionHandlerLib|OpenPlatformPkg/Platforms/APM/XGene/Modules/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+ CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+ DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+ ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+ ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+ TimerLib|OpenPlatformPkg/Platforms/APM/XGene/Modules/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+
+ # APM XGene specific libraries
+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+ EfiResetSystemLib|OpenPlatformPkg/Platforms/APM/XGene/Library/ResetSystemLib/ResetSystemLib.inf
+ NorFlashPlatformLib|OpenPlatformPkg/Platforms/APM/XGene/Library/APMXGeneNorFlashPlatformLib/APMXGeneNorFlashPlatformLib.inf
+ SerialPortExtLib|OpenPlatformPkg/Platforms/APM/XGene/Library/DWSerialPortLib/DWSerialPortExtLib.inf
+ RealTimeClockLib|OpenPlatformPkg/Platforms/APM/XGene/Library/APMXGeneRTCLib/APMXGeneRealTimeClockLib.inf
+ SlimproLib|OpenPlatformPkg/Platforms/APM/XGene/Library/SlimproLib/SlimproLib.inf
+
+ #
+ # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
+ # in the debugger will show load and unload commands for symbols. You can cut and paste this
+ # into the command window to load symbols. We should be able to use a script to do this, but
+ # the version of RVD I have does not support scripts accessing system memory.
+ #
+ #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
+ PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+ #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
+
+ SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+
+ # BDS Libraries
+ ArmBdsHelperLib|ArmPkg/Library/ArmBdsHelperLib/ArmBdsHelperLib.inf
+ BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+
+[LibraryClasses.common.SEC]
+ ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Sec/SecArmPlatformGlobalVariableLib.inf
+
+ DefaultExceptionHandlerLib|OpenPlatformPkg/Platforms/APM/XGene/Modules/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf
+
+!ifdef $(EDK2_SKIP_PEICORE)
+ PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+ ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+ LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+ HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+ PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+!endif
+
+ # Trustzone Support
+ ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.inf
+
+[LibraryClasses.common.PEI_CORE]
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf
+ PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.PEIM]
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf
+ PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Dxe/DxeArmPlatformGlobalVariableLib.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[LibraryClasses.ARM]
+ #
+ # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+ # This library provides the instrinsic functions generate by a given compiler.
+ # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+ #
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[LibraryClasses.AARCH64]
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+
+[BuildOptions]
+ RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+ #
+ # Control what commands are supported from the UI
+ # Turn these on and off to add features or save size
+ #
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
+
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+ # UEFI firmware is responsible to park the secondary cores on this platform.
+ # This PCD ensures the secondary cores are parked into the AArch64 Linux parking protocol.
+ gArmTokenSpaceGuid.PcdArmLinuxSpinTable|TRUE
+
+
+[PcdsFixedAtBuild.common]
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"AppliedMicro XGene"
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"APM-XGENE"
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|40
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+ # DEBUG_ASSERT_ENABLED 0x01
+ # DEBUG_PRINT_ENABLED 0x02
+ # DEBUG_CODE_ENABLED 0x04
+ # CLEAR_MEMORY_ENABLED 0x08
+ # ASSERT_BREAKPOINT_ENABLED 0x10
+ # ASSERT_DEADLOOP_ENABLED 0x20
+!if $(TARGET) == RELEASE
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+!endif
+
+ # DEBUG_INIT 0x00000001 // Initialization
+ # DEBUG_WARN 0x00000002 // Warnings
+ # DEBUG_LOAD 0x00000004 // Load events
+ # DEBUG_FS 0x00000008 // EFI File system
+ # DEBUG_POOL 0x00000010 // Alloc & Free's
+ # DEBUG_PAGE 0x00000020 // Alloc & Free's
+ # DEBUG_INFO 0x00000040 // Verbose
+ # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
+ # DEBUG_VARIABLE 0x00000100 // Variable
+ # DEBUG_BM 0x00000400 // Boot Manager
+ # DEBUG_BLKIO 0x00001000 // BlkIo Driver
+ # DEBUG_NET 0x00004000 // SNI Driver
+ # DEBUG_UNDI 0x00010000 // UNDI Driver
+ # DEBUG_LOADFILE 0x00020000 // UNDI Driver
+ # DEBUG_EVENT 0x00080000 // Event messages
+ # DEBUG_GCD 0x00100000 // Global Coherency Database changes
+ # DEBUG_CACHE 0x00200000 // Memory range cachability changes
+ # DEBUG_VERBOSE 0x00400000 // Detailed debug messages
+ # DEBUG_ERROR 0x80000000 // Error
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
+
+ #
+ # Optional feature to help prevent EFI memory map fragments
+ # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+ # Values are in EFI Pages (4K). DXE Core will make sure that
+ # at least this much of each type of memory can be allocated
+ # from a single memory range. This way you only end up with
+ # maximum of two fragements for each type in the memory map
+ # (the memory used, and the free memory that was prereserved
+ # but not used).
+ #
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+ #
+ # ARM Pcds
+ #
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000
+ gArmTokenSpaceGuid.PcdMaxTftpFileSize|0x08000000
+
+ #
+ # ARM PrimeCell
+ #
+
+ # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(9600,8,N,1)/VenPcAnsi()"
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(9600,8,N,1)/VenPcAnsi()"
+ gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|10
+
diff --git a/Platforms/APM/XGene/AcpiPlatformDxe/AcpiPlatform.c b/Platforms/APM/XGene/AcpiPlatformDxe/AcpiPlatform.c
new file mode 100644
index 0000000..12f04f5
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiPlatformDxe/AcpiPlatform.c
@@ -0,0 +1,84 @@
+/** @file
+ APM X-Gene ACPI Platform Driver
+
+ Copyright (c) 2014, Applied Micro Curcuit Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <PiDxe.h>
+#include <Guid/EventGroup.h>
+#include <Protocol/AcpiTable.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/AcpiSystemDescriptionTable.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/AcpiAml.h>
+#include "XGeneEthMAC.h"
+#include "XGeneCPU.h"
+
+/**
+ Notify function for event group EVT_SIGNAL_EXIT_BOOT_SERVICES. This is used
+ to configure the system clock and PHY accordingly.
+
+ @param[in] Event The Event that is being processed.
+ @param[in] Context The Event Context.
+
+**/
+VOID
+EFIAPI
+OnAcpiExitBootServices(
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ /* install APIC table */
+ XGeneInstallApicTable();
+
+ // Configure Ethernet MAC accordingly
+ XGeneEthMACInit();
+}
+
+/**
+ Entrypoint of Acpi Platform driver.
+
+ @param ImageHandle
+ @param SystemTable
+
+ @return EFI_SUCCESS
+ @return EFI_LOAD_ERROR
+ @return EFI_OUT_OF_RESOURCES
+
+**/
+EFI_STATUS
+EFIAPI
+AcpiPlatformEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_EVENT ExitBootServicesEvent;
+
+ Status = gBS->CreateEvent (
+ EVT_SIGNAL_EXIT_BOOT_SERVICES,
+ TPL_NOTIFY,
+ OnAcpiExitBootServices,
+ NULL,
+ &ExitBootServicesEvent);
+ ASSERT_EFI_ERROR(Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platforms/APM/XGene/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Platforms/APM/XGene/AcpiPlatformDxe/AcpiPlatformDxe.inf
new file mode 100644
index 0000000..f126346
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiPlatformDxe/AcpiPlatformDxe.inf
@@ -0,0 +1,78 @@
+## @file
+# X-Gene ACPI Platform Driver
+#
+# Copyright (c) 2014, Applied Micro Curcuit Corp. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = XGeneAcpiPlatform
+ FILE_GUID = e0829681-e9fa-4117-a8d7-84efadff863d
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = AcpiPlatformEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ AcpiPlatform.c
+ XGeneEthMAC.c
+ XGeneCPU.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ShellPkg/ShellPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ OpenPlatformPkg/Platforms/APM/XGene/APMXGene.dec
+
+[LibraryClasses]
+ UefiLib
+ DxeServicesLib
+ PcdLib
+ BaseMemoryLib
+ DebugLib
+ MemoryAllocationLib
+ UefiRuntimeServicesTableLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Guids]
+ gShellVariableGuid # ALWAYS_CONSUMED
+ gArmMpCoreInfoGuid
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED
+ gEfiAcpiSdtProtocolGuid # PROTOCOL ALWAYS_CONSUMED
+
+[FeaturePcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdBootingLinuxUEFI
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
+
+[Depex]
+ gEfiAcpiTableProtocolGuid
+
diff --git a/Platforms/APM/XGene/AcpiPlatformDxe/XGeneCPU.c b/Platforms/APM/XGene/AcpiPlatformDxe/XGeneCPU.c
new file mode 100755
index 0000000..4a9cb2e
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiPlatformDxe/XGeneCPU.c
@@ -0,0 +1,202 @@
+/** @file
+
+ APM X-Gene insert APIC table
+
+ Copyright (c) 2014, Applied Micro Curcuit Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ This driver is called to initialize the FW part of the PHY in preparation
+ for the OS.
+
+**/
+#include <Base.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiLib.h>
+#include <Library/PcdLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+#include <Protocol/AcpiTable.h>
+#include <Guid/Acpi.h>
+#include <IndustryStandard/Acpi51.h>
+
+#ifdef AARCH64_MP_PROTOCOL
+#define CPU_OFFSET 8
+#else
+#define CPU_OFFSET 0
+#endif
+
+EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE APICGicDistributerTemplate = {
+ EFI_ACPI_5_1_GICD,
+ sizeof(EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE),
+ 0,
+ 0,
+ FixedPcdGet32(PcdGicDistributorBase),
+ 0,
+ 0
+};
+
+EFI_ACPI_5_1_GIC_STRUCTURE APICProcessorRecordTemplate = {
+ EFI_ACPI_5_1_GIC,
+ sizeof(EFI_ACPI_5_1_GIC_STRUCTURE),
+ 0,
+ 0,
+ 0, /* need fill in */
+ EFI_ACPI_5_1_GIC_ENABLED,
+ 1,
+ 0,
+ 0, /* need fill in */
+ FixedPcdGet32(PcdGicInterruptInterfaceBase),
+ FixedPcdGet32(PcdGicInterruptInterfaceBase) + 0x40000, /* VGIC */
+ FixedPcdGet32(PcdGicInterruptInterfaceBase) + 0x20000, /* Hyp GIC */
+ 0x9,
+ FixedPcdGet32(PcdGicDistributorBase),
+ 0, /* need fill in */
+};
+
+EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER APICProcessorTableHeaderTemplate = {
+ {
+ EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ 0, /* need fill in */
+ EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, // Revision
+ 0x00, // Checksum will be updated at runtime
+ //
+ // It is expected that these values will be updated at EntryPoint.
+ //
+ {0}, // OEM ID is a 6 bytes long field
+ 0, // OEM Table ID(8 bytes long)
+ 0, // OEM Revision
+ 0, // Creator ID
+ 0, // Creator Revision
+ },
+ 0,
+ EFI_ACPI_5_1_PCAT_COMPAT
+};
+
+/**
+ This function calculates and updates an UINT8 checksum.
+
+ @param[in] Buffer Pointer to buffer to checksum
+ @param[in] Size Number of bytes to checksum
+
+**/
+VOID
+ApicAcpiTableChecksum (
+ IN UINT8 *Buffer,
+ IN UINTN Size
+ )
+{
+ UINTN ChecksumOffset;
+
+ ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum);
+
+ //
+ // Set checksum to 0 first.
+ //
+ Buffer[ChecksumOffset] = 0;
+
+ //
+ // Update checksum value.
+ //
+ Buffer[ChecksumOffset] = CalculateCheckSum8 (Buffer, Size);
+}
+
+EFI_STATUS
+XGeneInstallApicTable(VOID)
+{
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol;
+ ARM_PROCESSOR_TABLE *ArmProcessorTable;
+ ARM_CORE_INFO *ArmCoreInfoTable;
+ INTN Count, Count1;
+ UINTN Size;
+ EFI_STATUS Status;
+ UINTN ApicTableKey = 0;
+ EFI_ACPI_5_1_GIC_STRUCTURE *EntryPointer = NULL;
+ EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *GicDistributePointer = NULL;
+ EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *ApicTablePointer = NULL;
+ //
+ // Get AcpiTable Protocol.
+ //
+
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTableProtocol);
+ if (EFI_ERROR (Status))
+ return Status;
+
+ for (Count = 0; Count < gST->NumberOfTableEntries; Count++) {
+ if (CompareGuid (&gArmMpCoreInfoGuid, &(gST->ConfigurationTable[Count].VendorGuid))) {
+ ArmProcessorTable = (ARM_PROCESSOR_TABLE *)gST->ConfigurationTable[Count].VendorTable;
+ ArmCoreInfoTable = ArmProcessorTable->ArmCpus;
+
+ Size = sizeof(EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) +
+ ArmProcessorTable->NumberOfEntries * sizeof(EFI_ACPI_5_1_GIC_STRUCTURE) +
+ sizeof(EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE);
+
+ ApicTablePointer = (EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *)AllocateZeroPool(Size);
+ if (!ApicTablePointer)
+ return EFI_OUT_OF_RESOURCES;
+
+ EntryPointer = (EFI_ACPI_5_1_GIC_STRUCTURE *) ((UINT64)ApicTablePointer +
+ sizeof(EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER));
+
+ GicDistributePointer = (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *) ((UINT64)EntryPointer +
+ ArmProcessorTable->NumberOfEntries * sizeof(EFI_ACPI_5_1_GIC_STRUCTURE));
+
+ for (Count1 = 0; Count1 < ArmProcessorTable->NumberOfEntries; Count1++ ) {
+ CopyMem(&EntryPointer[Count1], &APICProcessorRecordTemplate, sizeof(EFI_ACPI_5_1_GIC_STRUCTURE));
+ EntryPointer[Count1].AcpiProcessorUid = (ArmCoreInfoTable[Count1].ClusterId) << 8 |
+ ArmCoreInfoTable[Count1].CoreId;
+ EntryPointer[Count1].CPUInterfaceNumber = Count1;
+ EntryPointer[Count1].MPIDR = EntryPointer[Count1].AcpiProcessorUid;
+ /* FixMe: Work around for non Redhat kernel */
+ if (PcdGet32 (PcdBootingLinuxUEFI) == 1)
+ EntryPointer[Count1].ParkedAddress = ArmCoreInfoTable[Count1].MailboxSetAddress + CPU_OFFSET;
+ else
+ EntryPointer[Count1].ParkedAddress = ArmCoreInfoTable[Count1].MailboxSetAddress;
+ }
+
+ CopyMem(ApicTablePointer, &APICProcessorTableHeaderTemplate,
+ sizeof(EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER));
+
+ ApicTablePointer->Header.Length = Size;
+ CopyMem(ApicTablePointer->Header.OemId, "APM ",
+ sizeof(ApicTablePointer->Header.OemId));
+ ApicTablePointer->Header.OemTableId = SIGNATURE_64('X', 'G', 'E', 'N', 'E', ' ', ' ', ' ');
+ ApicTablePointer->Header.OemRevision = 3;
+ ApicTablePointer->Header.CreatorId = PcdGet32 (PcdAcpiDefaultCreatorId);
+ ApicTablePointer->Header.CreatorRevision = PcdGet32 (PcdAcpiDefaultCreatorRevision);
+
+ CopyMem(GicDistributePointer, &APICGicDistributerTemplate,
+ sizeof(EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE));
+
+ ApicAcpiTableChecksum((UINT8 *)ApicTablePointer, ApicTablePointer->Header.Length);
+
+ Status = AcpiTableProtocol->InstallAcpiTable (
+ AcpiTableProtocol,
+ (VOID *)ApicTablePointer,
+ ApicTablePointer->Header.Length,
+ &ApicTableKey
+ );
+ if (EFI_ERROR (Status)) {
+ FreePool ((VOID *)ApicTablePointer);
+ return Status;
+ }
+ break;
+ }
+ }
+
+ if (Count == gST->NumberOfTableEntries)
+ return EFI_INVALID_PARAMETER;
+
+ return EFI_SUCCESS;
+}
diff --git a/Platforms/APM/XGene/AcpiPlatformDxe/XGeneCPU.h b/Platforms/APM/XGene/AcpiPlatformDxe/XGeneCPU.h
new file mode 100755
index 0000000..64904c4
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiPlatformDxe/XGeneCPU.h
@@ -0,0 +1,22 @@
+/*
+ * APM X-Gene insert APIC table
+ *
+ * Copyright (c) 2014, Applied Micro Circuits Corporation
+ * Author: Loc Ho <lho@apm.com>
+ *
+ * This program and the accompanying materials
+ *are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ */
+#ifndef __XGENECPU_H__
+#define __XGENECPU_H__
+
+EFI_STATUS
+XGeneInstallApicTable(VOID);
+
+#endif
+
diff --git a/Platforms/APM/XGene/AcpiPlatformDxe/XGeneEthMAC.c b/Platforms/APM/XGene/AcpiPlatformDxe/XGeneEthMAC.c
new file mode 100755
index 0000000..a2214d0
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiPlatformDxe/XGeneEthMAC.c
@@ -0,0 +1,512 @@
+/** @file
+ APM X-Gene Ethernet Firmware Initialization Driver
+
+ Copyright (c) 2014, Applied Micro Curcuit Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ This driver is called to initialize the FW part of the PHY in preparation
+ for the OS.
+
+**/
+
+#include <Guid/ShellVariableGuid.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <APMXGeneSocCsr.h>
+
+#include <PiDxe.h>
+#include <Guid/EventGroup.h>
+#include <Protocol/AcpiTable.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/AcpiSystemDescriptionTable.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/AcpiAml.h>
+
+#ifdef ACPI_DEBUG
+#define DBG(arg...) DEBUG((EFI_D_ERROR,## arg))
+#else
+#define DBG(arg...)
+#endif
+
+#define EFI_ACPI_MAX_NUM_TABLES 20
+#define DSDT_SIGNATURE 0x54445344
+/* For APM Ethernet driver */
+#define APM_ACPI_ETH_ID "APMC0D19"
+#define APM_ACPI_ETH_MAC_KEY "local-mac-address"
+
+/* For Open Source */
+#define ACPI_ETH_ID "APMC0D05"
+#define ACPI_ETH_MAC_KEY "mac-address"
+
+#define PREFIX_VARIABLE_NAME L"MAC"
+#define PREFIX_VARIABLE_NAME_COMPAT L"RGMII_MAC"
+#define MAC_MAX_LEN 30
+
+STATIC INTN FoundAPMEthernet = 0; //Set when first found APM Ethernet driver. Not open source driver
+
+EFI_STATUS GetEnvMAC(
+ IN UINTN MacNextID,
+ IN OUT CHAR16 *MACBuffer)
+{
+ EFI_STATUS Status;
+ CHAR16 MACEnv[MAC_MAX_LEN + 2];
+ UINTN Size;
+
+ //
+ // Get the MAC from PCD ENV
+ //
+ UnicodeSPrint(MACEnv, sizeof(MACEnv), L"%s%d", PREFIX_VARIABLE_NAME, MacNextID);
+
+ Size = MAC_MAX_LEN * sizeof(CHAR16);
+ Status = gRT->GetVariable(MACEnv, &gShellVariableGuid,
+ 0, &Size, (VOID *) MACBuffer);
+ if (EFI_ERROR(Status)) {
+ DBG("No MAC set for %S: %d\n", MACEnv, Status);
+ UnicodeSPrint(MACEnv, sizeof(MACEnv), L"%s%d", PREFIX_VARIABLE_NAME_COMPAT, MacNextID);
+ Size = MAC_MAX_LEN * sizeof(CHAR16);
+ Status = gRT->GetVariable(MACEnv, &gShellVariableGuid,
+ 0, &Size, (VOID *) MACBuffer);
+ if (EFI_ERROR(Status)) {
+ DBG("No MAC set for %S: %d\n", MACEnv, Status);
+ return Status;
+ }
+ }
+
+ DBG("%s %s\n", MACEnv, MACBuffer);
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS _SearchReplacePackageMACAddress(
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol,
+ IN EFI_ACPI_HANDLE ChildHandle,
+ IN UINTN Level,
+ IN OUT BOOLEAN *Found,
+ IN UINTN *MacNextID)
+{
+/*
+ * Name (_DSD, Package () {
+ * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ * Package () {
+ * Package (2) {"mac-address", Package (6) { 00, 11, 22, 33, 44, 55 }}
+ * Package (2) {"phy-channel", 0},
+ * Package (2) {"phy-mode", "rgmii"},
+ * Package (2) {"max-transfer-unit", 0x5dc}, // MTU of 1500
+ * Package (2) {"max-speed", 0x3e8}, // 1000 Mbps
+ * }
+ * })
+ */
+ EFI_STATUS Status;
+ EFI_ACPI_DATA_TYPE DataType;
+ CONST UINT8 *Data;
+ CONST VOID *Buffer;
+ UINTN DataSize;
+ UINTN Count;
+ EFI_ACPI_HANDLE CurrentHandle;
+ EFI_ACPI_HANDLE NextHandle;
+ CHAR16 MACBuffer[MAC_MAX_LEN];
+ CHAR16 StringByte[3];
+
+ DBG("In Level:%d\n", Level);
+ Status = EFI_SUCCESS;
+ for (CurrentHandle = NULL; ;) {
+ Status = AcpiTableProtocol->GetChild(ChildHandle, &CurrentHandle);
+ if (Level != 3 && (EFI_ERROR(Status) || CurrentHandle == NULL))
+ break;
+
+ Status = AcpiTableProtocol->GetOption(CurrentHandle, 0, &DataType, &Buffer, &DataSize);
+ Data = Buffer;
+ DBG("_DSD Child Subnode Store Op Code 0x%02X 0x%02X %02X\n",
+ DataSize, Data[0], DataSize > 1 ? Data[1] : 0);
+
+ if (Level < 2 && Data[0] != AML_PACKAGE_OP)
+ continue;
+
+ if (Level == 2 && Data[0] == AML_STRING_PREFIX) {
+ Status = AcpiTableProtocol->GetOption(CurrentHandle, 1, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ break;
+
+ DBG(" _DSD Child Subnode Store Op Code 0x%02X 0x%02X %02X\n",
+ DataSize, Data[0], DataSize > 1 ? Data[1] : 0);
+
+ Data = Buffer;
+ if (DataType != EFI_ACPI_DATA_TYPE_STRING
+ || AsciiStrCmp((CHAR8 *) Data, ACPI_ETH_MAC_KEY) != 0)
+ continue;
+
+ DBG("_DSD Key Type %d. Found MAC address key\n", DataType);
+
+ //
+ // We found the node.
+ //
+ *Found = TRUE;
+ continue;
+ }
+
+ if (Level == 3 && *Found) {
+ UINTN ColonCount = 0;
+ UINTN Value;
+
+ //Update the MAC
+ Status = GetEnvMAC((*MacNextID)++, MACBuffer);
+ if (EFI_ERROR(Status))
+ break;
+
+ for (Count = 0; Count < 6; Count++) {
+ StrnCpy(StringByte, MACBuffer + Count * 2 + ColonCount, 2);
+ StringByte[2] = '\0';
+ Value = StrHexToUintn(StringByte);
+
+ Status = AcpiTableProtocol->GetOption(CurrentHandle, 1, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ break;
+
+ Data = Buffer;
+ DBG(" _DSD Child Subnode Store Op Code 0x%02X 0x%02X %02X\n",
+ DataSize, Data[0], DataSize > 1 ? Data[1] : 0);
+
+ if (DataType != EFI_ACPI_DATA_TYPE_UINT)
+ break;
+
+ // only need one byte.
+ // FIXME: Assume the CPU is little endian
+ Status = AcpiTableProtocol->SetOption(CurrentHandle, 1, (VOID *)&Value, sizeof(UINT8));
+ if (EFI_ERROR(Status))
+ break;
+
+ Status = AcpiTableProtocol->GetChild(ChildHandle, &CurrentHandle);
+ if (EFI_ERROR(Status) || CurrentHandle == NULL)
+ break;
+
+ ColonCount++;
+ }
+
+ break;
+ }
+
+ if (Level > 3)
+ break;
+
+ //Search next package
+ AcpiTableProtocol->Open((VOID *) Buffer, &NextHandle);
+ Status = _SearchReplacePackageMACAddress(AcpiTableProtocol, NextHandle, Level + 1, Found, MacNextID);
+ AcpiTableProtocol->Close(NextHandle);
+ if (!EFI_ERROR(Status))
+ break;
+ }
+
+ return Status;
+}
+
+EFI_STATUS SearchReplacePackageMACAddress(
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol,
+ IN EFI_ACPI_HANDLE ChildHandle,
+ IN UINTN *MacNextID)
+{
+ BOOLEAN Found = FALSE;
+ UINTN Level = 0;
+
+ return _SearchReplacePackageMACAddress(AcpiTableProtocol, ChildHandle, Level, &Found, MacNextID);
+}
+
+EFI_STATUS XGeneProcessDSDTChild(
+ EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol,
+ EFI_ACPI_HANDLE ChildHandle, UINTN *MacNextID)
+{
+ EFI_STATUS Status;
+ EFI_ACPI_DATA_TYPE DataType;
+ CONST UINT8 *Data;
+ CONST VOID *Buffer;
+ UINTN DataSize;
+ EFI_ACPI_HANDLE DevHandle;
+ INTN Found = 0;
+
+ Status = AcpiTableProtocol->GetOption(ChildHandle, 0, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ return EFI_SUCCESS;
+
+ Data = Buffer;
+ //
+ // Skip all non-device type
+ //
+ if (DataSize != 2 || Data[0] != AML_EXT_OP || Data[1] != AML_EXT_DEVICE_OP)
+ return EFI_SUCCESS;
+
+ //
+ // Walk the device type node
+ //
+ for (DevHandle = NULL; ; ) {
+ Status = AcpiTableProtocol->GetChild(ChildHandle, &DevHandle);
+ if (EFI_ERROR(Status) || DevHandle == NULL)
+ break;
+
+ //
+ // Search for _HID with Ethernet ID
+ //
+ Status = AcpiTableProtocol->GetOption(DevHandle, 0, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ break;
+
+ Data = Buffer;
+ DBG("Data Type 0x%02X %02X\n", Data[0], DataSize > 1 ? Data[1] : 0);
+ if (DataSize == 1 && Data[0] == AML_NAME_OP) {
+ Status = AcpiTableProtocol->GetOption(DevHandle, 1, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ break;
+
+ Data = Buffer;
+ if (DataType == EFI_ACPI_DATA_TYPE_NAME_STRING) {
+ if (AsciiStrnCmp((CHAR8 *) Data, "_HID", 4) == 0) {
+ EFI_ACPI_HANDLE ValueHandle;
+
+ Status = AcpiTableProtocol->GetOption(DevHandle, 2, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ break;
+
+ if (DataType != EFI_ACPI_DATA_TYPE_CHILD)
+ continue;
+
+ AcpiTableProtocol->Open((VOID *) Buffer, &ValueHandle);
+ Status = AcpiTableProtocol->GetOption(ValueHandle, 1, &DataType, &Buffer, &DataSize);
+
+ Data = Buffer;
+ if (EFI_ERROR(Status) ||
+ DataType != EFI_ACPI_DATA_TYPE_STRING ||
+ (AsciiStrCmp((CHAR8 *) Data, APM_ACPI_ETH_ID) != 0 &&
+ AsciiStrCmp((CHAR8 *) Data, ACPI_ETH_ID) != 0)) {
+ AcpiTableProtocol->Close(ValueHandle);
+ Found = 0;
+ continue;
+ }
+
+ DBG("Found Ethernet device\n");
+ AcpiTableProtocol->Close(ValueHandle);
+ Found = 1;
+ } else if (Found == 1 && AsciiStrnCmp((CHAR8 *) Data, "_DSD", 4) == 0) {
+ //
+ // Patch MAC address for open source kernel
+ //
+ EFI_ACPI_HANDLE PkgHandle;
+ Status = AcpiTableProtocol->GetOption(DevHandle, 2, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ break;
+
+ if (DataType != EFI_ACPI_DATA_TYPE_CHILD)
+ continue;
+
+ //
+ // Open package data
+ //
+ AcpiTableProtocol->Open((VOID *) Buffer, &PkgHandle);
+ Status = AcpiTableProtocol->GetOption(PkgHandle, 0, &DataType, &Buffer, &DataSize);
+
+ Data = Buffer;
+ DBG("_DSD Subnode Store Op Code 0x%02X %02X\n",
+ Data[0], DataSize > 1 ? Data[1] : 0);
+
+ //
+ // Walk the _DSD node
+ //
+ if (DataSize == 1 && Data[0] == AML_PACKAGE_OP)
+ Status = SearchReplacePackageMACAddress(AcpiTableProtocol, PkgHandle, MacNextID);
+
+ AcpiTableProtocol->Close(PkgHandle);
+ }
+ }
+ } else if (DataSize == 1 && Data[0] == AML_METHOD_OP && Found) {
+ Status = AcpiTableProtocol->GetOption(DevHandle, 1, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ break;
+
+ if (DataType != EFI_ACPI_DATA_TYPE_NAME_STRING)
+ continue;
+
+ Data = Buffer;
+ if (AsciiStrnCmp((CHAR8 *) Data, "_DSM", 4) == 0) {
+ //
+ // Walk the _DSM node
+ //
+ EFI_ACPI_HANDLE DSMHandle;
+ EFI_ACPI_HANDLE PkgHandle;
+ EFI_ACPI_HANDLE KeyValueHandle;
+ for (DSMHandle = NULL; ; ) {
+ Status = AcpiTableProtocol->GetChild(DevHandle, &DSMHandle);
+ if (EFI_ERROR(Status) || DSMHandle == NULL)
+ break;
+
+ //
+ // Search for AML_STORE_OP type
+ //
+ Status = AcpiTableProtocol->GetOption(DSMHandle, 0, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ continue;
+
+ Data = Buffer;
+ if (DataSize != 1 || Data[0] != AML_STORE_OP)
+ continue;
+
+ Status = AcpiTableProtocol->GetOption(DSMHandle, 1, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ break;
+ DBG("_DSM Subnode Store Type %d\n", DataType);
+ if (DataType != EFI_ACPI_DATA_TYPE_CHILD)
+ continue;
+
+ //
+ // Open package data
+ //
+ AcpiTableProtocol->Open((VOID *) Buffer, &PkgHandle);
+ Status = AcpiTableProtocol->GetOption(PkgHandle, 0, &DataType, &Buffer, &DataSize);
+
+ Data = Buffer;
+ DBG("_DSM Subnode Store Op Code 0x%02X %02X\n",
+ Data[0], DataSize > 1 ? Data[1] : 0);
+ if (DataSize != 1 || Data[0] != AML_PACKAGE_OP) {
+ AcpiTableProtocol->Close(PkgHandle);
+ continue;
+ }
+
+ //
+ // Walk the package items
+ //
+ for (KeyValueHandle = NULL; ; ) {
+ CHAR16 MACValue16[30];
+ CHAR8 MACBuffer[30];
+
+ Status = AcpiTableProtocol->GetChild(PkgHandle, &KeyValueHandle);
+ if (EFI_ERROR(Status) || KeyValueHandle == NULL)
+ break;
+
+ Status = AcpiTableProtocol->GetOption(KeyValueHandle, 0, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ break;
+
+ Data = Buffer;
+ DBG("_DSM Key Value Op Code %d 0x%02X %02X\n",
+ DataType, Data[0], DataSize > 1 ? Data[1] : 0);
+ if (DataSize != 1 && Data[0] != AML_STRING_PREFIX)
+ continue;
+
+ Status = AcpiTableProtocol->GetOption(KeyValueHandle, 1, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ break;
+
+ Data = Buffer;
+ if (DataType != EFI_ACPI_DATA_TYPE_STRING
+ || AsciiStrCmp((CHAR8 *) Data, APM_ACPI_ETH_MAC_KEY) != 0)
+ continue;
+ DBG("_DSM Key Type %d. Found Mac address key\n", DataType);
+
+ if (!FoundAPMEthernet) {
+ FoundAPMEthernet = 1;
+ //Reset MacNextID
+ *MacNextID = 0;
+ }
+
+ //
+ // Get the MAC from PCD ENV
+ //
+ Status = GetEnvMAC((*MacNextID)++, MACValue16);
+ if (EFI_ERROR(Status)) {
+ continue;
+ }
+
+ UnicodeStrToAsciiStr(MACValue16, MACBuffer);
+
+ //
+ // We found the node. Update the MAC
+ //
+ Status = AcpiTableProtocol->GetChild(PkgHandle, &KeyValueHandle);
+ if (EFI_ERROR(Status) || KeyValueHandle == NULL)
+ break;
+
+ Status = AcpiTableProtocol->SetOption(KeyValueHandle, 1, MACBuffer, AsciiStrSize(MACBuffer));
+ break;
+ }
+ AcpiTableProtocol->Close(PkgHandle);
+ }
+ }
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+static EFI_STATUS XGeneProcessDSDT(
+ EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol,
+ EFI_ACPI_HANDLE TableHandle)
+{
+ EFI_STATUS Status;
+ EFI_ACPI_HANDLE ChildHandle;
+ UINTN MacEntryID;
+ //
+ // Parse table for device type
+ MacEntryID = 0;
+ for (ChildHandle = NULL; ; ) {
+ Status = AcpiTableProtocol->GetChild(TableHandle, &ChildHandle);
+ if (EFI_ERROR(Status))
+ break;
+ if (ChildHandle == NULL)
+ break;
+
+ XGeneProcessDSDTChild(AcpiTableProtocol, ChildHandle, &MacEntryID);
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS XGeneEthMACInit(void)
+{
+ EFI_STATUS Status;
+ EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol;
+ EFI_ACPI_SDT_HEADER *Table;
+ EFI_ACPI_TABLE_VERSION TableVersion;
+ UINTN TableKey;
+ EFI_ACPI_HANDLE TableHandle;
+ UINTN i;
+
+ DBG("Configure Ethernet MAC...\n");
+
+ //
+ // Find the AcpiTable protocol
+ Status = gBS->LocateProtocol(&gEfiAcpiSdtProtocolGuid, NULL, (VOID**) &AcpiTableProtocol);
+ if (EFI_ERROR(Status)) {
+ DBG("Unable to locate ACPI table protocol\n");
+ return EFI_SUCCESS;
+ }
+
+ //
+ // Search for DSDT Table
+ for (i = 0; i < EFI_ACPI_MAX_NUM_TABLES; i++) {
+ Status = AcpiTableProtocol->GetAcpiTable(i, &Table, &TableVersion, &TableKey);
+ if (EFI_ERROR(Status))
+ break;
+ if (Table->Signature != DSDT_SIGNATURE)
+ continue;
+
+ Status = AcpiTableProtocol->OpenSdt(TableKey, &TableHandle);
+ if (EFI_ERROR(Status))
+ break;
+
+ XGeneProcessDSDT(AcpiTableProtocol, TableHandle);
+
+ AcpiTableProtocol->Close(TableHandle);
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Platforms/APM/XGene/AcpiPlatformDxe/XGeneEthMAC.h b/Platforms/APM/XGene/AcpiPlatformDxe/XGeneEthMAC.h
new file mode 100755
index 0000000..379bb28
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiPlatformDxe/XGeneEthMAC.h
@@ -0,0 +1,21 @@
+/*
+ * APM X-Gene MAC Initalization
+ *
+ * Copyright (c) 2014, Applied Micro Circuits Corporation
+ * Author: Loc Ho <lho@apm.com>
+ *
+ * This program and the accompanying materials
+ *are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ */
+#ifndef __XGENEETHMAC_H__
+#define __XGENEETHMAC_H__
+
+EFI_STATUS XGeneEthMACInit(VOID);
+
+#endif
+
diff --git a/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/AcpiTables.inf b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/AcpiTables.inf
new file mode 100644
index 0000000..00c6681
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/AcpiTables.inf
@@ -0,0 +1,37 @@
+##
+# Component description file for PlatformAcpiTables module.
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformAcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+# Apic.asl
+ Facp.asl
+ Facs.asl
+ Dsdt.asl
+ Ssdt.asl
+ Gtdt.asl
+ Dbg2.asl
+ Spcr.asl
+ Mcfg.asl
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git a/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Apic.asl b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Apic.asl
new file mode 100644
index 0000000..f0e9c36
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Apic.asl
@@ -0,0 +1,190 @@
+/**
+ * Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+ *
+ * This program and the accompanying materials are licensed and made
+ * available under the terms and conditions of the BSD License which
+ * accompanies this distribution. The full text of the license may be
+ * found at * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ * APIC Table for X-Gene Processor
+ *
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ **/
+
+[0004] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[0004] Table Length : 0000028C
+[0001] Revision : 03
+[0001] Checksum : 00
+[0006] Oem ID : "APM "
+[0008] Oem Table ID : "XGENE "
+[0004] Oem Revision : 00000003
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20140724
+
+[0004] Local Apic Address : 00000000
+[0004] Flags (decoded below) : 00000000
+ PC-AT Compatibility : 0
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 4C
+[0002] Reserved : 0000
+[0004] CPU Interface Number : 00000000
+[0004] Processor UID : 00000000
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[0004] Parking Protocol Version : 00000001
+[0004] Performance Interrupt : 0000001A
+[0008] Parked Address : 0x00004000008000
+[0008] Base Address : 00000000780A0000
+[0008] Virtual GIC Base Address : 00000000780E0000
+[0008] Hypervisor GIC Base Address : 00000000780C0000
+[0004] Virtual GIC Interrupt : 00000009
+[0008] Redistributor Base Address : 0000000078090000
+[0008] ARM MPIDR : 0000000000000000
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 4C
+[0002] Reserved : 0000
+[0004] CPU Interface Number : 00000000
+[0004] Processor UID : 00000001
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[0004] Parking Protocol Version : 00000001
+[0004] Performance Interrupt : 0000001A
+[0008] Parked Address : 0000004000009000
+[0008] Base Address : 00000000780A0000
+[0008] Virtual GIC Base Address : 00000000780E0000
+[0008] Hypervisor GIC Base Address : 00000000780C0000
+[0004] Virtual GIC Interrupt : 00000009
+[0008] Redistributor Base Address : 0000000078090000
+[0008] ARM MPIDR : 0000000000000001
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 4C
+[0002] Reserved : 0000
+[0004] CPU Interface Number : 00000000
+[0004] Processor UID : 00000100
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[0004] Parking Protocol Version : 00000001
+[0004] Performance Interrupt : 0000001A
+[0008] Parked Address : 000000400000a000
+[0008] Base Address : 00000000780A0000
+[0008] Virtual GIC Base Address : 00000000780E0000
+[0008] Hypervisor GIC Base Address : 00000000780C0000
+[0004] Virtual GIC Interrupt : 00000009
+[0008] Redistributor Base Address : 0000000078090000
+[0008] ARM MPIDR : 0000000000000100
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 4C
+[0002] Reserved : 0000
+[0004] CPU Interface Number : 00000000
+[0004] Processor UID : 00000101
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[0004] Parking Protocol Version : 00000001
+[0004] Performance Interrupt : 0000001A
+[0008] Parked Address : 000000400000b000
+[0008] Base Address : 00000000780A0000
+[0008] Virtual GIC Base Address : 00000000780E0000
+[0008] Hypervisor GIC Base Address : 00000000780C0000
+[0004] Virtual GIC Interrupt : 00000009
+[0008] Redistributor Base Address : 0000000078090000
+[0008] ARM MPIDR : 0000000000000101
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 4C
+[0002] Reserved : 0000
+[0004] CPU Interface Number : 00000000
+[0004] Processor UID : 00000200
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[0004] Parking Protocol Version : 00000001
+[0004] Performance Interrupt : 0000001A
+[0008] Parked Address : 000000400000c000
+[0008] Base Address : 00000000780A0000
+[0008] Virtual GIC Base Address : 00000000780E0000
+[0008] Hypervisor GIC Base Address : 00000000780C0000
+[0004] Virtual GIC Interrupt : 00000009
+[0008] Redistributor Base Address : 0000000078090000
+[0008] ARM MPIDR : 0000000000000200
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 4C
+[0002] Reserved : 0000
+[0004] CPU Interface Number : 00000000
+[0004] Processor UID : 00000201
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[0004] Parking Protocol Version : 00000001
+[0004] Performance Interrupt : 0000001A
+[0008] Parked Address : 000000400000d000
+[0008] Base Address : 00000000780A0000
+[0008] Virtual GIC Base Address : 00000000780E0000
+[0008] Hypervisor GIC Base Address : 00000000780C0000
+[0004] Virtual GIC Interrupt : 00000009
+[0008] Redistributor Base Address : 0000000078090000
+[0008] ARM MPIDR : 0000000000000201
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 4C
+[0002] Reserved : 0000
+[0004] CPU Interface Number : 00000000
+[0004] Processor UID : 00000300
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[0004] Parking Protocol Version : 00000001
+[0004] Performance Interrupt : 0000001A
+[0008] Parked Address : 000000400000e000
+[0008] Base Address : 00000000780A0000
+[0008] Virtual GIC Base Address : 00000000780E0000
+[0008] Hypervisor GIC Base Address : 00000000780C0000
+[0004] Virtual GIC Interrupt : 00000009
+[0008] Redistributor Base Address : 0000000078090000
+[0008] ARM MPIDR : 0000000000000300
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 4C
+[0002] Reserved : 0000
+[0004] CPU Interface Number : 00000000
+[0004] Processor UID : 00000301
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[0004] Parking Protocol Version : 00000001
+[0004] Performance Interrupt : 0000001A
+[0008] Parked Address : 000000400000f000
+[0008] Base Address : 00000000780A0000
+[0008] Virtual GIC Base Address : 00000000780E0000
+[0008] Hypervisor GIC Base Address : 00000000780C0000
+[0004] Virtual GIC Interrupt : 00000009
+[0008] Redistributor Base Address : 0000000078090000
+[0008] ARM MPIDR : 0000000000000301
+
+[0001] Subtable Type : 0C [Generic Interrupt Distributor]
+[0001] Length : 18
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000000
+[0008] Base Address : 0000000078090000
+[0004] Interrupt Base : 00000000
+[0004] Reserved : 00000000
diff --git a/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Dbg2.asl b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Dbg2.asl
new file mode 100644
index 0000000..584cafc
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Dbg2.asl
@@ -0,0 +1,74 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20131115-64 [Dec 3 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [DBG2] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "DBG2" [Debug Port table type 2]
+[0004] Table Length : 000000B2
+[0001] Revision : 00
+[0001] Checksum : BA
+[0006] Oem ID : "APMC0D"
+[0008] Oem Table ID : "XGENEDBG"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20131115
+
+[0004] Info Offset : 0000002C
+[0004] Info Count : 00000002
+
+[0001] Revision : 00
+[0002] Length : 003F
+[0001] Register Count : 01
+[0002] Namepath Length : 0009
+[0002] Namepath Offset : 0036
+[0002] OEM Data Length : 0000 [Optional field not present]
+[0002] OEM Data Offset : 0000 [Optional field not present]
+[0002] Port Type : 8000
+[0002] Port Subtype : 0001
+[0002] Reserved : 0000
+[0002] Base Address Offset : 0016
+[0002] Address Size Offset : 002E
+
+[0012] Receive Buffer Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 20
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 03 [Dword access]
+[0008] Address : 000000001C021000
+
+[0004] Address Size : 00000008
+
+[0017] Namepath : "\\_SB_.AHBC.URT1"
+
+[0001] Revision : 00
+[0002] Length : 003F
+[0001] Register Count : 01
+[0002] Namepath Length : 0009
+[0002] Namepath Offset : 0036
+[0002] OEM Data Length : 0000 [Optional field not present]
+[0002] OEM Data Offset : 0000 [Optional field not present]
+[0002] Port Type : 8000
+[0002] Port Subtype : 0001
+[0002] Reserved : 0000
+[0002] Base Address Offset : 0016
+[0002] Address Size Offset : 002E
+
+[0012] Receive Buffer Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 20
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 03 [Dword access]
+[0008] Address : 000000001C020000
+
+[0004] Address Size : 00000008
+
+[0017] Namepath : "\\_SB_.AHBC.URT0"
+
+[0016] OEM Data : 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
+
+[0016] OEM Data : 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
+
diff --git a/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Dsdt.asl b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Dsdt.asl
new file mode 100644
index 0000000..8f6f607
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Dsdt.asl
@@ -0,0 +1,3139 @@
+/**
+ * Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ **/
+
+DefinitionBlock("Dsdt.aml", "DSDT", 0x05, "APM ", "APM88xxxx", 1) {
+
+//Operation Region For Power Control and Power Good
+ OperationRegion(\PGUD, SystemMemory, 0x17000078, 4)
+ OperationRegion(\PCTL, SystemMemory, 0x1700007C, 4)
+ Field(\PGUD, DWordAcc, NoLock, Preserve) {
+ SOCG, 1,
+ L3CG, 1,
+ PD0G, 1,
+ PD1G, 1,
+ PD2G, 1,
+ PD3G, 1
+ }
+ Field(\PCTL, DWordAcc, NoLock, Preserve) {
+ SOCC, 1,
+ L3CC, 1,
+ PD0C, 1,
+ PD1C, 1,
+ PD2C, 1,
+ PD3C, 1
+ }
+
+//SOC VRM resource, power domain for SOC
+ PowerResource(SCVR, 2, 0) {
+ Method(_STA) {
+ Return (NAnd(SOCC, One))
+ }
+ Method(_ON) {
+ Store(One, SOCC)
+ Sleep(10)
+ }
+ Method(_OFF) {
+ Store(Zero, SOCC)
+ Sleep(10)
+ }
+ }//SCVR
+
+////////////////////////////////////////////////////////////////////////////////
+//System Sleep States
+
+ Name(\_S0, Package(){0x00000000, 0x00000000})
+ Name(\_S1, Package(){0x00000001, 0x00000000})
+ Name(\_S2, Package(){0x00000002, 0x00000000})
+
+////////////////////////////////////////////////////////////////////////////////
+//Processor
+ Device(\_SB.CPU0) {
+
+ Name(_UID, 0)
+ Name(_HID, "ACPI0007")
+ Method(_STA) {
+ Return (One)
+ }
+
+//Clock Domain Object
+ Name(_CDM, 0) //Domain 0
+
+ Method(_PSC) {
+ Return (0)
+ } //_PSC
+
+//Sleeping state correlation
+ Name(_S1D, 3)
+ Name(_S2D, 4)
+ Name(_S3D, 6)
+
+//Performance Control
+ Name(_PCT, Package() {
+ ResourceTemplate() {Register(SystemIO, 32, 0, 0x10550000, 3)},
+ ResourceTemplate() {Register(SystemIO, 32, 0, 0x10550004, 3)}
+ }) //_PCT
+//Performance States
+ Name(_PSS, Package() {
+ Package() {
+ 2400, //frequency MHz
+ 2500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x10, //Control value
+ 0x20, //Status value
+ }, //P0
+ Package() {
+ 2400, //frequency MHz
+ 2500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x11, //Control value
+ 0x21, //Status value
+ }, //P1
+ Package() {
+ 1200, //frequency MHz
+ 1500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x12, //Control value
+ 0x22, //Status value
+ }, //P2
+ Package() {
+ 800, //frequency MHz
+ 1000, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x13, //Control value
+ 0x23, //Status value
+ }, //P3
+ Package() {
+ 600, //frequency MHz
+ 800, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x14, //Control value
+ 0x24, //Status value
+ } //P4
+ }) //_PSS
+//Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 0, 0xFC, 2}
+ }) //Domain 0
+
+//C states
+ Name(_CST, Package() {
+ 2,
+ Package() { //C1 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10550014, 3)},
+ 1,
+ 0, //latency usec
+ 2500 //power mW
+ }, //C1 state
+ Package() { //C2 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)},
+ 2,
+ 0, //latency usec
+ 0 //power mW
+ }, //C2 state
+ Package() { //C3 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10550018, 3)},
+ 3,
+ 200000, //latency usec
+ 1800 //power mW
+ }, //C3 state
+ Package() { //C4 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x1055001C, 3)},
+ 4,
+ 500000, //latency usec
+ 1000 //power mW
+ }, //C4 state
+ Package() { //C5 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)},
+ 5,
+ 0, //latency usec
+ 0 //power mW
+ }, //C5 state
+ Package() { //C6 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10550020, 3)},
+ 6,
+ 10000000, //latency usec
+ 0 //power mW
+ }, //C6 state
+
+ }) //_CST
+//C state dependency
+ Name(_CSD, Package() {
+ Package() {6, 0, 1, 0xFC, 2, 2},
+ Package() {6, 0, 5, 0xFC, 8, 3},
+ Package() {6, 0, 6, 0xFC, 8, 5},
+ }) //_CSD
+
+ }//CPU0
+////////////////////////////////////////////////////////////////////////////////
+//Processor
+ Device(\_SB.CPU1) {
+
+ Name(_UID, 1)
+ Name(_HID, "ACPI0007")
+ Method(_STA) {
+ Return (One)
+ }
+
+//Clock Domain Object
+ Name(_CDM, 0) //Domain 0
+
+ Method(_PSC) {
+ Return (0)
+ } //_PSC
+
+//Sleeping state correlation
+ Name(_S1D, 3)
+ Name(_S2D, 4)
+ Name(_S3D, 6)
+
+//Performance Control
+ Name(_PCT, Package() {
+ ResourceTemplate() {Register(SystemIO, 32, 0, 0x10551000, 3)},
+ ResourceTemplate() {Register(SystemIO, 32, 0, 0x10551004, 3)}
+ }) //_PCT
+//Performance States
+ Name(_PSS, Package() {
+ Package() {
+ 2400, //frequency MHz
+ 2500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x10, //Control value
+ 0x20, //Status value
+ }, //P0
+ Package() {
+ 2400, //frequency MHz
+ 2500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x11, //Control value
+ 0x21, //Status value
+ }, //P1
+ Package() {
+ 1200, //frequency MHz
+ 1500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x12, //Control value
+ 0x22, //Status value
+ }, //P2
+ Package() {
+ 800, //frequency MHz
+ 1000, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x13, //Control value
+ 0x23, //Status value
+ }, //P3
+ Package() {
+ 600, //frequency MHz
+ 800, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x14, //Control value
+ 0x24, //Status value
+ } //P4
+ }) //_PSS
+//Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 0, 0xFC, 2}
+ }) //Domain 0
+
+//C states
+ Name(_CST, Package() {
+ 2,
+ Package() { //C1 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10551014, 3)},
+ 1,
+ 0, //latency usec
+ 2500 //power mW
+ }, //C1 state
+ Package() { //C2 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)},
+ 2,
+ 0, //latency usec
+ 0 //power mW
+ }, //C2 state
+ Package() { //C3 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10551018, 3)},
+ 3,
+ 200000, //latency usec
+ 1800 //power mW
+ }, //C3 state
+ Package() { //C4 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x1055101C, 3)},
+ 4,
+ 500000, //latency usec
+ 1000 //power mW
+ }, //C4 state
+ Package() { //C5 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)},
+ 5,
+ 0, //latency usec
+ 0 //power mW
+ }, //C5 state
+ Package() { //C6 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10551020, 3)},
+ 6,
+ 10000000, //latency usec
+ 0 //power mW
+ }, //C6 state
+
+ }) //_CST
+//C state dependency
+ Name(_CSD, Package() {
+ Package() {6, 0, 1, 0xFC, 2, 2},
+ Package() {6, 0, 5, 0xFC, 8, 3},
+ Package() {6, 0, 6, 0xFC, 8, 5},
+ }) //_CSD
+
+ //Return the MADT table
+ //FIXME, need to figure out where to get table location from
+ //Method(_MAT) {
+ //}
+
+ }//CPU1
+////////////////////////////////////////////////////////////////////////////////
+//Processor
+ Device(\_SB.CPU2) {
+
+ Name(_UID, 0x100)
+ Name(_HID, "ACPI0007")
+ Method(_STA) {
+ Return (One)
+ }
+
+//Clock Domain Object
+ Name(_CDM, 1) //Domain 1
+
+ Method(_PSC) {
+ Return (0)
+ } //_PSC
+
+//Sleeping state correlation
+ Name(_S1D, 3)
+ Name(_S2D, 4)
+ Name(_S3D, 6)
+
+//Performance Control
+ Name(_PCT, Package() {
+ ResourceTemplate() {Register(SystemIO, 32, 0, 0x10552000, 3)},
+ ResourceTemplate() {Register(SystemIO, 32, 0, 0x10552004, 3)}
+ }) //_PCT
+//Performance States
+ Name(_PSS, Package() {
+ Package() {
+ 2400, //frequency MHz
+ 2500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x10, //Control value
+ 0x20, //Status value
+ }, //P0
+ Package() {
+ 2400, //frequency MHz
+ 2500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x11, //Control value
+ 0x21, //Status value
+ }, //P1
+ Package() {
+ 1200, //frequency MHz
+ 1500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x12, //Control value
+ 0x22, //Status value
+ }, //P2
+ Package() {
+ 800, //frequency MHz
+ 1000, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x13, //Control value
+ 0x23, //Status value
+ }, //P3
+ Package() {
+ 600, //frequency MHz
+ 800, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x14, //Control value
+ 0x24, //Status value
+ } //P4
+ }) //_PSS
+//Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 1, 0xFC, 2}
+ }) //Domain 1
+
+//C states
+ Name(_CST, Package() {
+ 2,
+ Package() { //C1 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10552014, 3)},
+ 1,
+ 0, //latency usec
+ 2500 //power mW
+ }, //C1 state
+ Package() { //C2 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)},
+ 2,
+ 0, //latency usec
+ 0 //power mW
+ }, //C2 state
+ Package() { //C3 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10552018, 3)},
+ 3,
+ 200000, //latency usec
+ 1800 //power mW
+ }, //C3 state
+ Package() { //C4 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x1055201C, 3)},
+ 4,
+ 500000, //latency usec
+ 1000 //power mW
+ }, //C4 state
+ Package() { //C5 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)},
+ 5,
+ 0, //latency usec
+ 0 //power mW
+ }, //C5 state
+ Package() { //C6 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10552020, 3)},
+ 6,
+ 10000000, //latency usec
+ 0 //power mW
+ }, //C6 state
+
+ }) //_CST
+//C state dependency
+ Name(_CSD, Package() {
+ Package() {6, 0, 2, 0xFC, 2, 2},
+ Package() {6, 0, 5, 0xFC, 8, 3},
+ Package() {6, 0, 6, 0xFC, 8, 5},
+ }) //_CSD
+
+ //Return the MADT table
+ //FIXME, need to figure out where to get table location from
+ //Method(_MAT) {
+ //}
+
+ }//CPU2
+////////////////////////////////////////////////////////////////////////////////
+//Processor
+ Device(\_SB.CPU3) {
+
+ Name(_UID, 0x101)
+ Name(_HID, "ACPI0007")
+ Method(_STA) {
+ Return (One)
+ }
+
+//Clock Domain Object
+ Name(_CDM, 1) //Domain 1
+
+ Method(_PSC) {
+ Return (0)
+ } //_PSC
+
+//Sleeping state correlation
+ Name(_S1D, 3)
+ Name(_S2D, 4)
+ Name(_S3D, 6)
+
+//Performance Control
+ Name(_PCT, Package() {
+ ResourceTemplate() {Register(SystemIO, 32, 0, 0x10553000, 3)},
+ ResourceTemplate() {Register(SystemIO, 32, 0, 0x10553004, 3)}
+ }) //_PCT
+//Performance States
+ Name(_PSS, Package() {
+ Package() {
+ 2400, //frequency MHz
+ 2500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x10, //Control value
+ 0x20, //Status value
+ }, //P0
+ Package() {
+ 2400, //frequency MHz
+ 2500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x11, //Control value
+ 0x21, //Status value
+ }, //P1
+ Package() {
+ 1200, //frequency MHz
+ 1500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x12, //Control value
+ 0x22, //Status value
+ }, //P2
+ Package() {
+ 800, //frequency MHz
+ 1000, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x13, //Control value
+ 0x23, //Status value
+ }, //P3
+ Package() {
+ 600, //frequency MHz
+ 800, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x14, //Control value
+ 0x24, //Status value
+ } //P4
+ }) //_PSS
+//Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 1, 0xFC, 2}
+ }) //Domain 1
+
+//C states
+ Name(_CST, Package() {
+ 2,
+ Package() { //C1 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10553014, 3)},
+ 1,
+ 0, //latency usec
+ 2500 //power mW
+ }, //C1 state
+ Package() { //C2 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)},
+ 2,
+ 0, //latency usec
+ 0 //power mW
+ }, //C2 state
+ Package() { //C3 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10553018, 3)},
+ 3,
+ 200000, //latency usec
+ 1800 //power mW
+ }, //C3 state
+ Package() { //C4 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x1055301C, 3)},
+ 4,
+ 500000, //latency usec
+ 1000 //power mW
+ }, //C4 state
+ Package() { //C5 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)},
+ 5,
+ 0, //latency usec
+ 0 //power mW
+ }, //C5 state
+ Package() { //C6 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10553020, 3)},
+ 6,
+ 10000000, //latency usec
+ 0 //power mW
+ }, //C6 state
+
+ }) //_CST
+//C state dependency
+ Name(_CSD, Package() {
+ Package() {6, 0, 2, 0xFC, 2, 2},
+ Package() {6, 0, 5, 0xFC, 8, 3},
+ Package() {6, 0, 6, 0xFC, 8, 5},
+ }) //_CSD
+
+ //Return the MADT table
+ //FIXME, need to figure out where to get table location from
+ //Method(_MAT) {
+ //}
+
+ }//CPU3
+////////////////////////////////////////////////////////////////////////////////
+//Processor
+ Device(\_SB.CPU4) {
+
+ Name(_UID, 0x200)
+ Name(_HID, "ACPI0007")
+ Method(_STA) {
+ Return (One)
+ }
+
+//Clock Domain Object
+ Name(_CDM, 2) //Domain 2
+
+ Method(_PSC) {
+ Return (0)
+ } //_PSC
+
+//Sleeping state correlation
+ Name(_S1D, 3)
+ Name(_S2D, 4)
+ Name(_S3D, 6)
+
+//Performance Control
+ Name(_PCT, Package() {
+ ResourceTemplate() {Register(SystemIO, 32, 0, 0x10554000, 3)},
+ ResourceTemplate() {Register(SystemIO, 32, 0, 0x10554004, 3)}
+ }) //_PCT
+//Performance States
+ Name(_PSS, Package() {
+ Package() {
+ 2400, //frequency MHz
+ 2500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x10, //Control value
+ 0x20, //Status value
+ }, //P0
+ Package() {
+ 2400, //frequency MHz
+ 2500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x11, //Control value
+ 0x21, //Status value
+ }, //P1
+ Package() {
+ 1200, //frequency MHz
+ 1500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x12, //Control value
+ 0x22, //Status value
+ }, //P2
+ Package() {
+ 800, //frequency MHz
+ 1000, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x13, //Control value
+ 0x23, //Status value
+ }, //P3
+ Package() {
+ 600, //frequency MHz
+ 800, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x14, //Control value
+ 0x24, //Status value
+ } //P4
+ }) //_PSS
+//Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 2, 0xFC, 2}
+ }) //Domain 2
+
+//C states
+ Name(_CST, Package() {
+ 2,
+ Package() { //C1 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10554014, 3)},
+ 1,
+ 0, //latency usec
+ 2500 //power mW
+ }, //C1 state
+ Package() { //C2 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)},
+ 2,
+ 0, //latency usec
+ 0 //power mW
+ }, //C2 state
+ Package() { //C3 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10554018, 3)},
+ 3,
+ 200000, //latency usec
+ 1800 //power mW
+ }, //C3 state
+ Package() { //C4 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x1055401C, 3)},
+ 4,
+ 500000, //latency usec
+ 1000 //power mW
+ }, //C4 state
+ Package() { //C5 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)},
+ 5,
+ 0, //latency usec
+ 0 //power mW
+ }, //C5 state
+ Package() { //C6 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10554020, 3)},
+ 6,
+ 10000000, //latency usec
+ 0 //power mW
+ }, //C6 state
+
+ }) //_CST
+//C state dependency
+ Name(_CSD, Package() {
+ Package() {6, 0, 3, 0xFC, 2, 2},
+ Package() {6, 0, 5, 0xFC, 8, 3},
+ Package() {6, 0, 6, 0xFC, 8, 5},
+ }) //_CSD
+
+ //Return the MADT table
+ //FIXME, need to figure out where to get table location from
+ //Method(_MAT) {
+ //}
+
+ }//CPU4
+////////////////////////////////////////////////////////////////////////////////
+//Processor
+ Device(\_SB.CPU5) {
+
+ Name(_UID, 0x201)
+ Name(_HID, "ACPI0007")
+ Method(_STA) {
+ Return (One)
+ }
+
+//Clock Domain Object
+ Name(_CDM, 2) //Domain 2
+
+ Method(_PSC) {
+ Return (0)
+ } //_PSC
+
+//Sleeping state correlation
+ Name(_S1D, 3)
+ Name(_S2D, 4)
+ Name(_S3D, 6)
+
+//Performance Control
+ Name(_PCT, Package() {
+ ResourceTemplate() {Register(SystemIO, 32, 0, 0x10555000, 3)},
+ ResourceTemplate() {Register(SystemIO, 32, 0, 0x10555004, 3)}
+ }) //_PCT
+//Performance States
+ Name(_PSS, Package() {
+ Package() {
+ 2400, //frequency MHz
+ 2500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x10, //Control value
+ 0x20, //Status value
+ }, //P0
+ Package() {
+ 2400, //frequency MHz
+ 2500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x11, //Control value
+ 0x21, //Status value
+ }, //P1
+ Package() {
+ 1200, //frequency MHz
+ 1500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x12, //Control value
+ 0x22, //Status value
+ }, //P2
+ Package() {
+ 800, //frequency MHz
+ 1000, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x13, //Control value
+ 0x23, //Status value
+ }, //P3
+ Package() {
+ 600, //frequency MHz
+ 800, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x14, //Control value
+ 0x24, //Status value
+ } //P4
+ }) //_PSS
+//Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 2, 0xFC, 2}
+ }) //Domain 2
+
+//C states
+ Name(_CST, Package() {
+ 2,
+ Package() { //C1 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10555014, 3)},
+ 1,
+ 0, //latency usec
+ 2500 //power mW
+ }, //C1 state
+ Package() { //C2 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)},
+ 2,
+ 0, //latency usec
+ 0 //power mW
+ }, //C2 state
+ Package() { //C3 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10555018, 3)},
+ 3,
+ 200000, //latency usec
+ 1800 //power mW
+ }, //C3 state
+ Package() { //C4 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x1055501C, 3)},
+ 4,
+ 500000, //latency usec
+ 1000 //power mW
+ }, //C4 state
+ Package() { //C5 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)},
+ 5,
+ 0, //latency usec
+ 0 //power mW
+ }, //C5 state
+ Package() { //C6 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10555020, 3)},
+ 6,
+ 10000000, //latency usec
+ 0 //power mW
+ }, //C6 state
+
+ }) //_CST
+//C state dependency
+ Name(_CSD, Package() {
+ Package() {6, 0, 3, 0xFC, 2, 2},
+ Package() {6, 0, 5, 0xFC, 8, 3},
+ Package() {6, 0, 6, 0xFC, 8, 5},
+ }) //_CSD
+
+ //Return the MADT table
+ //FIXME, need to figure out where to get table location from
+ //Method(_MAT) {
+ //}
+
+ }//CPU5
+////////////////////////////////////////////////////////////////////////////////
+//Processor
+ Device(\_SB.CPU6) {
+
+ Name(_UID, 0x300)
+ Name(_HID, "ACPI0007")
+ Method(_STA) {
+ Return (One)
+ }
+
+//Clock Domain Object
+ Name(_CDM, 3) //Domain 3
+
+ Method(_PSC) {
+ Return (0)
+ } //_PSC
+
+//Sleeping state correlation
+ Name(_S1D, 3)
+ Name(_S2D, 4)
+ Name(_S3D, 6)
+
+//Performance Control
+ Name(_PCT, Package() {
+ ResourceTemplate() {Register(SystemIO, 32, 0, 0x10556000, 3)},
+ ResourceTemplate() {Register(SystemIO, 32, 0, 0x10556004, 3)}
+ }) //_PCT
+//Performance States
+ Name(_PSS, Package() {
+ Package() {
+ 2400, //frequency MHz
+ 2500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x10, //Control value
+ 0x20, //Status value
+ }, //P0
+ Package() {
+ 2400, //frequency MHz
+ 2500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x11, //Control value
+ 0x21, //Status value
+ }, //P1
+ Package() {
+ 1200, //frequency MHz
+ 1500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x12, //Control value
+ 0x22, //Status value
+ }, //P2
+ Package() {
+ 800, //frequency MHz
+ 1000, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x13, //Control value
+ 0x23, //Status value
+ }, //P3
+ Package() {
+ 600, //frequency MHz
+ 800, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x14, //Control value
+ 0x24, //Status value
+ } //P4
+ }) //_PSS
+//Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 3, 0xFC, 2}
+ }) //Domain 3
+
+//C states
+ Name(_CST, Package() {
+ 2,
+ Package() { //C1 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10556014, 3)},
+ 1,
+ 0, //latency usec
+ 2500 //power mW
+ }, //C1 state
+ Package() { //C2 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)},
+ 2,
+ 0, //latency usec
+ 0 //power mW
+ }, //C2 state
+ Package() { //C3 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10556018, 3)},
+ 3,
+ 200000, //latency usec
+ 1800 //power mW
+ }, //C3 state
+ Package() { //C4 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x1055601C, 3)},
+ 4,
+ 500000, //latency usec
+ 1000 //power mW
+ }, //C4 state
+ Package() { //C5 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)},
+ 5,
+ 0, //latency usec
+ 0 //power mW
+ }, //C5 state
+ Package() { //C6 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10556020, 3)},
+ 6,
+ 10000000, //latency usec
+ 0 //power mW
+ }, //C6 state
+
+ }) //_CST
+//C state dependency
+ Name(_CSD, Package() {
+ Package() {6, 0, 4, 0xFC, 2, 2},
+ Package() {6, 0, 5, 0xFC, 8, 3},
+ Package() {6, 0, 6, 0xFC, 8, 5},
+ }) //_CSD
+
+ //Return the MADT table
+ //FIXME, need to figure out where to get table location from
+ //Method(_MAT) {
+ //}
+
+ }//CPU6
+////////////////////////////////////////////////////////////////////////////////
+//Processor
+ Device(\_SB.CPU7) {
+
+ Name(_UID, 0x301)
+ Name(_HID, "ACPI0007")
+ Method(_STA) {
+ Return (One)
+ }
+
+//Clock Domain Object
+ Name(_CDM, 3) //Domain 3
+
+ Method(_PSC) {
+ Return (0)
+ } //_PSC
+
+//Sleeping state correlation
+ Name(_S1D, 3)
+ Name(_S2D, 4)
+ Name(_S3D, 6)
+
+//Performance Control
+ Name(_PCT, Package() {
+ ResourceTemplate() {Register(SystemIO, 32, 0, 0x10557000, 3)},
+ ResourceTemplate() {Register(SystemIO, 32, 0, 0x10557004, 3)}
+ }) //_PCT
+//Performance States
+ Name(_PSS, Package() {
+ Package() {
+ 2400, //frequency MHz
+ 2500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x10, //Control value
+ 0x20, //Status value
+ }, //P0
+ Package() {
+ 2400, //frequency MHz
+ 2500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x11, //Control value
+ 0x21, //Status value
+ }, //P1
+ Package() {
+ 1200, //frequency MHz
+ 1500, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x12, //Control value
+ 0x22, //Status value
+ }, //P2
+ Package() {
+ 800, //frequency MHz
+ 1000, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x13, //Control value
+ 0x23, //Status value
+ }, //P3
+ Package() {
+ 600, //frequency MHz
+ 800, //Power milli watts
+ 10, //Latency usec
+ 10, //Bus master latency usec
+ 0x14, //Control value
+ 0x24, //Status value
+ } //P4
+ }) //_PSS
+//Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 3, 0xFC, 2}
+ }) //Domain 3
+
+//C states
+ Name(_CST, Package() {
+ 2,
+ Package() { //C1 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10557014, 3)},
+ 1,
+ 0, //latency usec
+ 2500 //power mW
+ }, //C1 state
+ Package() { //C2 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)},
+ 2,
+ 0, //latency usec
+ 0 //power mW
+ }, //C2 state
+ Package() { //C3 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10557018, 3)},
+ 3,
+ 200000, //latency usec
+ 1800 //power mW
+ }, //C3 state
+ Package() { //C4 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x1055701C, 3)},
+ 4,
+ 500000, //latency usec
+ 1000 //power mW
+ }, //C4 state
+ Package() { //C5 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x00000000, 3)},
+ 5,
+ 0, //latency usec
+ 0 //power mW
+ }, //C5 state
+ Package() { //C6 state
+ ResourceTemplate() {Register(SystemMemory, 32, 0, 0x10557020, 3)},
+ 6,
+ 10000000, //latency usec
+ 0 //power mW
+ }, //C6 state
+
+ }) //_CST
+//C state dependency
+ Name(_CSD, Package() {
+ Package() {6, 0, 4, 0xFC, 2, 2},
+ Package() {6, 0, 5, 0xFC, 8, 3},
+ Package() {6, 0, 6, 0xFC, 8, 5},
+ }) //_CSD
+
+ //Return the MADT table
+ //FIXME, need to figure out where to get table location from
+ //Method(_MAT) {
+ //}
+
+ }//CPU7
+
+///////////////////////////////////////////////////////////////////////////////
+// Method DTGP
+ Method (DTGP, 5, NotSerialized) {
+ If (LEqual (Arg0, Buffer (0x10) {
+ /* UUID: a706b112-bf0b-48d2-9fa3-95591a3c4c06 */
+ /* 0000 */ 0xA7, 0x06, 0xB1, 0x12, 0xBF, 0x0B, 0x48, 0xD2,
+ /* 0008 */ 0x9f, 0xA3, 0x95, 0x59, 0x1A, 0x3C, 0x4C, 0x06
+ }))
+
+ {
+ If (LEqual (Arg1, 0x01)) {
+ If (LEqual (Arg2, 0x00)) {
+ Store (Buffer (0x01) {
+ 0x03
+ }, Arg4)
+ Return (0x01)
+ }
+ If (LEqual (Arg2, 0x01)) {
+ Return (0x01)
+ }
+ }
+ }
+
+ Store (Buffer (0x01) {
+ 0x00
+ }, Arg4)
+ Return (0x00)
+ }
+
+///////////////////////////////////////////////////////////////////////////////
+// PMU
+ Device(\_SB.PMU0) {
+ Name(_HID, "LNRO0007") // Device Identification Objects
+ Name(_DDN, "PMU0")
+ Name(_UID, "PMU0")
+ Name(_STR, Unicode("PMU"))
+ Name(_CID, "LNRO0007")
+ Name(_CRS, ResourceTemplate() {
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x1C }
+ })
+ }
+
+///////////////////////////////////////////////////////////////////////////////
+// SLIMpro Device
+ Device(\_SB.SLIM) {
+ Name(_HID, "APMC0D01") // Device Identification Objects
+ Name(_DDN, "SLIM")
+ Name(_UID, "SLIM")
+ Name(_STR, Unicode("SLIMpro Device"))
+ Name(_CID, "APMC0D01")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x10540000, 0xa100, )
+ Memory32Fixed(ReadWrite, 0x17000000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x17001000, 0x1000, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x20 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x21 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x22 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x23 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x24 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x25 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x26 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x27 }
+ })
+ Name(DBST, 0x0000) // Doorbell start index
+ Name(DBEN, 0x0007) // Doorbell end index
+ Name(DBRT, 0x0005) // Doorbell retry count
+ Name(DBEV, 0x0007) // Doorbell event
+ Name(DBIC, 0x0000) // Doorbell I2C
+ } //SLIM
+
+///////////////////////////////////////////////////////////////////////////////
+// EDAC MC0 Device
+ Device(\_SB.EMC0) {
+ Name(_HID, "APMC0D10") // Device Identification Objects
+ Name(_DDN, "EMC0")
+ Name(_UID, "EMC0")
+ Name(_STR, Unicode("EDAC MC0 Device"))
+ Name(_ADR, 0x7E800000)
+ Name(_CID, "APMC0D10")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x78800000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E200000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E700000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E720000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E800000, 0x1000, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x40 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x41 }
+ })
+ } //EDAC MC0 Device
+
+// EDAC MC1 Device
+ Device(\_SB.EMC1) {
+ Name(_HID, "APMC0D10") // Device Identification Objects
+ Name(_DDN, "EMC1")
+ Name(_UID, "EMC1")
+ Name(_STR, Unicode("EDAC MC1 Device"))
+ Name(_ADR, 0x7E840000)
+ Name(_CID, "APMC0D10")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x78800000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E200000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E700000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E720000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E840000, 0x1000, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x40 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x41 }
+ })
+ } //EDAC MC1 Device
+
+// EDAC MC2 Device
+ Device(\_SB.EMC2) {
+ Name(_HID, "APMC0D10") // Device Identification Objects
+ Name(_DDN, "EMC2")
+ Name(_UID, "EMC2")
+ Name(_STR, Unicode("EDAC MC2 Device"))
+ Name(_ADR, 0x7E880000)
+ Name(_CID, "APMC0D10")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x78800000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E200000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E700000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E720000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E880000, 0x1000, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x40 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x41 }
+ })
+ } //EDAC MC2 Device
+
+// EDAC MC3 Device
+ Device(\_SB.EMC3) {
+ Name(_HID, "APMC0D10") // Device Identification Objects
+ Name(_DDN, "EMC3")
+ Name(_UID, "EMC3")
+ Name(_STR, Unicode("EDAC MC3 Device"))
+ Name(_ADR, 0x7E8C0000)
+ Name(_CID, "APMC0D10")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x78800000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E200000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E700000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E720000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E8C0000, 0x1000, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x40 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x41 }
+ })
+ } //EDAC MC3 Device
+
+///////////////////////////////////////////////////////////////////////////////
+// EDAC L3 Device
+ Device(\_SB.EL3) {
+ Name(_HID, "APMC0D11") // Device Identification Objects
+ Name(_DDN, "EL3")
+ Name(_UID, "EL3")
+ Name(_STR, Unicode("EDAC L3 Device"))
+ Name(_ADR, 0x7E600000)
+ Name(_CID, "APMC0D11")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x78800000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E600000, 0x1000, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x40 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x41 }
+ })
+ } //EDAC L3 Device
+
+///////////////////////////////////////////////////////////////////////////////
+// EDAC PMD0 Device
+ Device(\_SB.PMD0) {
+ Name(_HID, "APMC0D12") // Device Identification Objects
+ Name(_DDN, "PMD0")
+ Name(_UID, "PMD0")
+ Name(_STR, Unicode("EDAC PMD0 Device"))
+ Name(_ADR, 0x7C000000)
+ Name(_CID, "APMC0D12")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x78800000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7C000000, 0x200000, )
+ Memory32Fixed(ReadWrite, 0x1054A000, 0x10, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x40 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x41 }
+ })
+ } //EDAC PMD0 Device
+
+// EDAC PMD1 Device
+ Device(\_SB.PMD1) {
+ Name(_HID, "APMC0D12") // Device Identification Objects
+ Name(_DDN, "PMD1")
+ Name(_UID, "PMD1")
+ Name(_STR, Unicode("EDAC PMD1 Device"))
+ Name(_ADR, 0x7C200000)
+ Name(_CID, "APMC0D12")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x78800000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7C200000, 0x200000, )
+ Memory32Fixed(ReadWrite, 0x1054A000, 0x10, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x40 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x41 }
+ })
+ } //EDAC PMD1 Device
+
+// EDAC PMD2 Device
+ Device(\_SB.PMD2) {
+ Name(_HID, "APMC0D12") // Device Identification Objects
+ Name(_DDN, "PMD2")
+ Name(_UID, "PMD2")
+ Name(_STR, Unicode("EDAC PMD2 Device"))
+ Name(_ADR, 0x7C400000)
+ Name(_CID, "APMC0D12")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x78800000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7C400000, 0x200000, )
+ Memory32Fixed(ReadWrite, 0x1054A000, 0x10, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x40 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x41 }
+ })
+ } //EDAC PMD2 Device
+
+// EDAC PMD3 Device
+ Device(\_SB.PMD3) {
+ Name(_HID, "APMC0D12") // Device Identification Objects
+ Name(_DDN, "PMD3")
+ Name(_UID, "PMD3")
+ Name(_STR, Unicode("EDAC PMD3 Device"))
+ Name(_ADR, 0x7C600000)
+ Name(_CID, "APMC0D12")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x78800000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7C600000, 0x200000, )
+ Memory32Fixed(ReadWrite, 0x1054A000, 0x10, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x40 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x41 }
+ })
+ } //EDAC PMD3 Device
+
+///////////////////////////////////////////////////////////////////////////////
+// EDAC SOC Device
+ Device(\_SB.ESOC) {
+ Name(_HID, "APMC0D13") // Device Identification Objects
+ Name(_DDN, "ESOC")
+ Name(_UID, "ESOC")
+ Name(_STR, Unicode("EDAC SOC Device"))
+ Name(_ADR, 0x7E930000)
+ Name(_CID, "APMC0D13")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x78800000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E930000, 0x1000, )
+ Memory32Fixed(ReadWrite, 0x7E000000, 0x1000, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x40 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x41 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x47 }
+ })
+ } //EDAC SOC Device
+
+///////////////////////////////////////////////////////////////////////////////
+// GPIO
+ Device(\_SB.GP00) {
+ Name(_HID, "APMC0D07") // Device Identification Objects
+ Name(_CID, "APMC0D07")
+ Name(_UID, "GPIO0")
+ Name(_STR, Unicode("GPIO Device"))
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1C024000, 0x1000)
+ })
+ } //GP00 Device
+
+///////////////////////////////////////////////////////////////////////////////
+// GPIOSB
+ Device(\_SB.GPSB) {
+ Name(_HID, "APMC0D15") // Device Identification Objects
+ Name(_CID, "APMC0D15")
+ Name(_UID, "GPIOSB")
+ Name(_STR, Unicode("GPIOSB Device"))
+ Method(_DSM, 4, NotSerialized) {
+ Store (Package (6) {
+ "ngpio", "22",
+ "nirq", "6",
+ "irq_pins", "8 9 10 11 12 13",
+ }, Local0)
+ Return (Local0)
+ }
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x17001000, 0x400)
+ Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive) { 0x48 }
+ Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive) { 0x49 }
+ Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive) { 0x4A }
+ Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive) { 0x4B }
+ Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive) { 0x4C }
+ Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive) { 0x4D }
+ })
+ } //GPIOSBDevice
+
+///////////////////////////////////////////////////////////////////////////////
+//AHBC Bus
+ // AHBC Device
+ Device(\_SB.AHBC) {
+ OperationRegion(SRST, SystemMemory, 0x1F2AC000, 4)
+ OperationRegion(CLKE, SystemMemory, 0x1F2AC004, 4)
+ OperationRegion(SRRM, SystemMemory, 0x1F2AD070, 4)
+ OperationRegion(RD2F, SystemMemory, 0x1F2AE014, 4)
+ Field(SRST, DWordAcc, NoLock, Preserve) {
+ ACSR, 1,
+ SDRS, 1,
+ IORS, 1,
+ U0RS, 1,
+ U1RS, 1,
+ U2RS, 1,
+ U3RS, 1,
+ S0RS, 1,
+ S1RS, 1,
+ APRS, 1
+ }
+ Field(CLKE, DWordAcc, NoLock, Preserve) {
+ ACCE, 1,
+ SDCE, 1,
+ IOCE, 1,
+ U0CE, 1,
+ U1CE, 1,
+ U2CE, 1,
+ U3CE, 1,
+ S0CE, 1,
+ S1CE, 1,
+ APCE, 1
+ }
+ Field(SRRM, DWordAcc, NoLock, Preserve) {
+ RMSH, 32
+ }
+ Field(RD2F, DWordAcc, NoLock, Preserve) {
+ RSV9, 1,
+ RDFL, 1,
+ RSVA, 30
+ }
+
+ // Device Identification Objects
+ Name(_HID, "APMC0D06")
+ Name(_DDN, "AHBC")
+ Name(_UID, "AHBC")
+ Name(_CID, "APMC0D06")
+ Name(_STR, Unicode("AHBC Peripheral Bus"))
+
+ // Device Configuration Objects
+ // Device Status
+ Method(_STA) {
+ if (LOr(LOr(NAnd(ACSR, One), NAnd(APRS, One)),
+ LOr(LEqual(ACCE, Zero), LEqual(APCE, Zero)))) {
+ Return (1)
+ }
+ Return (3)
+ } //_STA
+
+ // Device current resources, two registers
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1f2a0000, 0x80000, )
+ Memory32Fixed(ReadWrite, 0x1c000200, 0x100, )
+ })
+
+//==============================================================================
+
+ //UART0 Device Controller
+ Device(URT0) {
+ //Device Identification Objects
+ Name(_HID, "APMC0D08")
+ Name(_DDN, "URT0")
+ Name(_UID, "URT0")
+ Name(_STR, Unicode("APM X-Gene UART0 Controller"))
+
+ Name(_ADR, 0x1C020000)
+ Name(_CID, "NS16550")
+
+ //Disable Device Method
+ Method(_DIS) {
+ Store(Zero, U0CE)
+ Store(One, U0RS)
+ } //_DIS
+
+ //Device Status
+ Method(_STA) {
+ if (LOr(NAnd(U0RS, One), LEqual(U0CE, Zero))) {
+ Return (1)
+ }
+ Return (3)
+ } //_STA
+
+ //Device Power Management Methods
+ //D0 State, ON
+ Method(_PS0) {
+ Store(One, U0CE)
+ Store(Zero, U0RS)
+ } //_PS0
+ //D3 State, OFF
+ Method(_PS3) {
+ Store(Zero, U0CE)
+ Store(One, U0RS)
+ }//_PS3
+ //Current Power State
+ Method(_PSC) {
+ if (LOr(NAnd(U0RS, One), LEqual(U0CE, Zero))) {
+ Return (3)
+ }
+ Return (0)
+
+ } //_PSC
+ //Power Resources Needed in D0 State
+ Name(_PR0, Package() {SCVR})
+ //Can be put to D3 state when in S1 state
+ Name(_S1D, 3)
+ //Lowest D-State supported in S1 to support wakeup
+ Name(_S1W, 0)
+ //Inform OSPM to use _S1W instead of _S1D when used for wake up
+ Name(_PRW, Package() { 0x0, 0x3 })
+
+ //Device Current Resource Settings
+ //UART0 Generates an interrupt
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1C020000, 0x100)
+ UARTSerialBus(
+ 115200, //Baud Rate
+ DataBitsEight, //Bits-per-byte
+ StopBitsOne, //StopBits
+ 0x00, //Lines in use
+ LittleEndian,
+ ParityTypeNone,
+ FlowControlNone,
+ 16, //Rx Buffer size
+ 16, //Tx Buffer size
+ "URT0", //This resource for UART0
+ 0,
+ ResourceConsumer,
+ U0DT
+ )
+ Interrupt(ResourceProducer, Level, ActiveHigh,
+ Exclusive) {108}
+ })
+ } //URT0
+
+ //UART1 Device Controller
+ Device(URT1) {
+ //Device Identification Objects
+ Name(_HID, "APMC0D08")
+ Name(_DDN, "URT1")
+ Name(_UID, "URT1")
+ Name(_STR, Unicode("APM88xxxx UART1 Controller"))
+
+ Name(_ADR, 0x1C021000)
+ Name(_CID, "NS16550")
+
+ //Disable Device Method
+ Method(_DIS) {
+ Store(Zero, U1CE)
+ Store(One, U1RS)
+ } //_DIS
+
+ //Device Status
+ Method(_STA) {
+ if (LOr(NAnd(U1RS, One), LEqual(U1CE, Zero))) {
+ Return (1)
+ }
+ Return (3)
+ } //_STA
+
+ //Device Power Management Methods
+ //D0 State, ON
+ Method(_PS0) {
+ Store(One, U1CE)
+ Store(Zero, U1RS)
+ } //_PS0
+ //D3 State, OFF
+ Method(_PS3) {
+ Store(Zero, U1CE)
+ Store(One, U1RS)
+ }//_PS3
+ //Current Power State
+ Method(_PSC) {
+ if (LOr(NAnd(U1RS, One), LEqual(U1CE, Zero))) {
+ Return (3)
+ }
+ Return (0)
+
+ } //_PSC
+ //Power Resources Needed in D0 State
+ Name(_PR0, Package() {SCVR})
+ //Can be put to D3 state when in S1 state
+ Name(_S1D, 3)
+ //Lowest D-State supported in S1 to support wakeup
+ Name(_S1W, 0)
+ //Inform OSPM to use _S1W instead of _S1D when used for wake up
+ Name(_PRW, Package() { 0x0, 0x3 })
+
+ //Device Current Resource Settings
+ //UART1 Generates an interrupt
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1C021000, 0x100)
+ UARTSerialBus(
+ 115200, //Baud Rate
+ DataBitsEight, //Bits-per-byte
+ StopBitsOne, //StopBits
+ 0x00, //Lines in use
+ LittleEndian,
+ ParityTypeNone,
+ FlowControlNone,
+ 16, //Rx Buffer size
+ 16, //Tx Buffer size
+ "URT1", //This resource for UART0
+ 0,
+ ResourceConsumer,
+ U1DT
+ )
+ Interrupt(ResourceProducer, Level, ActiveHigh,
+ Exclusive) {109}
+ })
+ } //URT1
+//==============================================================================
+ //SPI0 Device Controller
+ Device(SPI0) {
+
+ //Device Identification Objects
+ Name(_HID, "SPI00000")
+ Name(_DDN, "SPI0")
+ Name(_UID, "SPI0")
+ Name(_STR, Unicode("APM88xxxx SPI0 Controller"))
+
+ //Disable Device Method
+ Method(_DIS) {
+ Store(Zero, S0CE)
+ Store(One, S0RS)
+ } //_DIS
+
+ //Device Status
+ Method(_STA) {
+ if (LOr(NAnd(S0RS, One), LEqual(S0CE, Zero))) {
+ Return (1)
+ }
+ Return (3)
+ } //_STA
+
+ //Device Power Management Methods
+ //D0 State, ON
+ Method(_PS0) {
+ Store(One, S0CE)
+ Store(Zero, S0RS)
+ } //_PS0
+ //D3 State, OFF
+ Method(_PS3) {
+ Store(Zero, S0CE)
+ Store(One, S0RS)
+ }//_PS3
+ //Current Power State
+ Method(_PSC) {
+ if (LOr(NAnd(S0RS, One), LEqual(S0CE, Zero))) {
+ Return (3)
+ }
+ Return (0)
+
+ } //_PSC
+ //Power Resources Needed in D0 State
+ Name(_PR0, Package() {SCVR})
+ //Can be put to D3 state when in S1 state
+ Name(_S1D, 3)
+
+ //Device Current Resource Settings
+ //SPI0 Generates an interrupt
+ Name(_CRS, ResourceTemplate() {
+ Interrupt(ResourceProducer, Level, ActiveHigh,
+ Exclusive) {106}
+ })
+ }//SPI0
+
+ //SPI0 CS0 connection resource
+ Name(SP00, ResourceTemplate() {
+ SPISerialBus(
+ 1, //Slave select CS0 (_ADR)
+ PolarityHigh, //Polarity of CS0 output(_DPL)
+ FourWireMode, //(_MOD)
+ 8, //8-bit frame(_LEN)
+ ControllerInitiated, //(_SLV)
+ 12500000, //Speed Hz (_SPE)
+ ClockPolarityHigh, //(_POL)
+ ClockPhaseSecond, //(_PHA)
+ "SPI0", //Controller
+ 0,
+ ResourceConsumer,
+ )
+ })//SP00
+
+ //SPI0 CS1 connection resource
+ Name(SP01, ResourceTemplate() {
+ SPISerialBus(
+ 2, //Slave select CS0 (_ADR)
+ PolarityHigh, //Polarity of CS0 output(_DPL)
+ FourWireMode, //(_MOD)
+ 8, //8-bit frame(_LEN)
+ ControllerInitiated, //(_SLV)
+ 12500000, //Speed Hz (_SPE)
+ ClockPolarityHigh, //(_POL)
+ ClockPhaseSecond, //(_PHA)
+ "SPI0", //Controller
+ 0,
+ ResourceConsumer,
+ )
+ })//SP01
+
+ //SPI0 CS2 connection resource
+ Name(SP02, ResourceTemplate() {
+ SPISerialBus(
+ 4, //Slave select CS0 (_ADR)
+ PolarityHigh, //Polarity of CS0 output(_DPL)
+ FourWireMode, //(_MOD)
+ 8, //8-bit frame(_LEN)
+ ControllerInitiated, //(_SLV)
+ 12500000, //Speed Hz (_SPE)
+ ClockPolarityHigh, //(_POL)
+ ClockPhaseSecond, //(_PHA)
+ "SPI0", //Controller
+ 0,
+ ResourceConsumer,
+ )
+ })//SP02
+
+//==============================================================================
+ //SPI1 Device Controller
+ Device(SPI1) {
+
+ //Device Identification Objects
+ Name(_HID, "SPI10000")
+ Name(_DDN, "SPI1")
+ Name(_UID, "SPI1")
+ Name(_STR, Unicode("APM88xxxx SPI1 Controller"))
+
+ //Disable Device Method
+ Method(_DIS) {
+ Store(Zero, S1CE)
+ Store(One, S1RS)
+ } //_DIS
+
+ //Device Status
+ Method(_STA) {
+ if (LOr(NAnd(S1RS, One), LEqual(S1CE, Zero))) {
+ Return (1)
+ }
+ Return (3)
+ } //_STA
+
+ //Device Power Management Methods
+ //D0 State, ON
+ Method(_PS0) {
+ Store(One, S1CE)
+ Store(Zero, S1RS)
+ } //_PS0
+ //D3 State, OFF
+ Method(_PS3) {
+ Store(Zero, S1CE)
+ Store(One, S1RS)
+ }//_PS3
+ //Current Power State
+ Method(_PSC) {
+ if (LOr(NAnd(S1RS, One), LEqual(S1CE, Zero))) {
+ Return (3)
+ }
+ Return (0)
+
+ } //_PSC
+ //Power Resources Needed in D0 State
+ Name(_PR0, Package() {SCVR})
+ //Can be put to D3 state when in S1 state
+ Name(_S1D, 3)
+
+ //Device Current Resource Settings
+ //SPI0 Generates an interrupt
+ Name(_CRS, ResourceTemplate() {
+ Interrupt(ResourceProducer, Level, ActiveHigh,
+ Exclusive) {107}
+ })
+ }//SPI1
+
+ //SPI1 CS0 connection resource
+ Name(SP10, ResourceTemplate() {
+ SPISerialBus(
+ 1, //Slave select CS0 (_ADR)
+ PolarityHigh, //Polarity of CS0 output(_DPL)
+ FourWireMode, //(_MOD)
+ 8, //8-bit frame(_LEN)
+ ControllerInitiated, //(_SLV)
+ 12500000, //Speed Hz (_SPE)
+ ClockPolarityHigh, //(_POL)
+ ClockPhaseSecond, //(_PHA)
+ "SPI1", //Controller
+ 0,
+ ResourceConsumer,
+ )
+ })//SP10
+
+ //SPI1 CS1 connection resource
+ Name(SP11, ResourceTemplate() {
+ SPISerialBus(
+ 2, //Slave select CS0 (_ADR)
+ PolarityHigh, //Polarity of CS0 output(_DPL)
+ FourWireMode, //(_MOD)
+ 8, //8-bit frame(_LEN)
+ ControllerInitiated, //(_SLV)
+ 12500000, //Speed Hz (_SPE)
+ ClockPolarityHigh, //(_POL)
+ ClockPhaseSecond, //(_PHA)
+ "SPI1", //Controller
+ 0,
+ ResourceConsumer,
+ )
+ })//SP11
+
+ //SPI1 CS2 connection resource
+ Name(SP12, ResourceTemplate() {
+ SPISerialBus(
+ 4, //Slave select CS0 (_ADR)
+ PolarityHigh, //Polarity of CS0 output(_DPL)
+ FourWireMode, //(_MOD)
+ 8, //8-bit frame(_LEN)
+ ControllerInitiated, //(_SLV)
+ 12500000, //Speed Hz (_SPE)
+ ClockPolarityHigh, //(_POL)
+ ClockPhaseSecond, //(_PHA)
+ "SPI1", //Controller
+ 0,
+ ResourceConsumer,
+ )
+ })//SP12
+
+ // SDIO0
+ Device(SDM0) {
+ Name(_HID, "APMC0D0C") // Device Identification Objects
+ Name(_CID, "APMC0D0C")
+ Name(_STR, Unicode("APM X-Gene SDHCI Controller"))
+
+ Method(_STA) {
+ Return (One)
+ }
+
+ Name(_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x1C000000, 0x100)
+ Memory32Fixed (ReadWrite, 0x1f2a0000, 0x1000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake) { 0x69 }
+ })
+
+ OperationRegion(CPL0, SystemMemory, 0x1F2A0024, 4)
+ OperationRegion(CPH0, SystemMemory, 0x1F2A0028, 4)
+ OperationRegion(CFG0, SystemMemory, 0x1F2A0000, 4)
+ Field(CPL0, DWordAcc, NoLock, Preserve) {
+ TOCF, 6,
+ TOCU, 1,
+ BACF, 8,
+ MXBL, 2,
+ EMBS, 1,
+ ADM2, 1,
+ RSV1, 1,
+ HSST, 1,
+ SDMA, 1,
+ SURS, 1,
+ VS33, 1,
+ VS30, 1,
+ VS18, 1,
+ BS64, 1,
+ ASIS, 1,
+ SLTY, 2,
+ RSV2, 2
+ }
+ Field(CPH0, DWordAcc, NoLock, Preserve) {
+ DTAS, 1,
+ DTCS, 1,
+ DTDS, 1,
+ TCRT, 4,
+ TU50, 1,
+ MODE, 2,
+ CLMU, 8,
+ SPIM, 1,
+ SPIB, 1,
+ RSV3, 12
+ }
+ Field(CFG0, DWordAcc, NoLock, Preserve) {
+ RXWG, 4,
+ TXWG, 4,
+ PWMO, 4,
+ RSV4, 3,
+ WBRD, 1,
+ RSV5, 1,
+ RDPR, 2,
+ RDCH, 1,
+ RSV6, 1,
+ WRPR, 2,
+ WRCH, 1,
+ RSV7, 8
+ }
+
+ // Device Power Management Methods
+ // D0 State, ON
+ Method(_PS0) {
+ // Configure the capability of the core
+ Store(0x30, TOCF) // Time out 48MHz
+ Store(One, TOCU) // Clock unit MHz
+ Store(50, BACF) // 50MHz clock
+ Store(Zero, MXBL) // 512B block size
+ Store(Zero, EMBS) // No extend media support
+ Store(Zero, ADM2) // No ADMA2 support
+ Store(Zero, RSV1)
+ Store(One, HSST) // High speed support
+ Store(One, SDMA) // SDMA support
+ Store(One, SURS) // Suspend/resume support
+ Store(One, VS33) // 3.3 voltage support
+ Store(One, VS30) // 3.0 voltage support
+ Store(Zero, VS18) // No 1.8 voltage support
+ Store(Zero, BS64) // No 64-bit
+ Store(Zero, ASIS) // Async Int
+ Store(Zero, SLTY) // Removable media
+ Store(0, RSV2)
+
+ Store(One, DTAS) // Type A support
+ Store(One, DTCS) // Type C support
+ Store(One, DTDS) // Type D support
+ Store(One, TCRT) // 1 seconds timer counter
+ Store(One, TU50) // SDR50 tuning
+ Store(Zero, MODE) // Return mode 1
+ Store(Zero, CLMU) // Clock multipler
+ Store(Zero, SPIM) // No SPI mode
+ Store(Zero, SPIB) // No SPI block mode
+ Store(Zero, RSV3) // Reserved
+
+ // Configure coherency
+ Store(0xf, RXWG) // Tx weight
+ Store(0xf, TXWG) // Tx weight
+ Store(0x1, PWMO) // PW Max outstanding
+ Store(0x0, RSV4) // Reserved
+ Store(0x1, WBRD) // Write block Read
+ Store(0x0, RSV5) // Reserved
+ Store(0x2, RDPR) // Read AXI sideband prio
+ Store(0x1, RDCH) // Read Coherent
+ Store(0x0, RSV6) // Reserved
+ Store(0x2, WRPR) // Write AXI sideband prio
+ Store(0x1, WRCH) // Write Coherent
+ Store(0x0, RSV7) // Reserved
+
+ // Configure PIN Mux
+ // NOTE: Default for GPIO is SD function
+
+ // Enable clock and CSR
+ Store(One, SDCE) // Enable the clock
+ Store(Zero, SDRS) // Enable the CSR
+
+ // Enable AHBC read to flush
+ Store(1, RDFL) // Enable read to flush
+
+ // Remove RAM from shutdown
+ Store(Zero, RMSH) // Release from shutdown
+ Sleep(1) // Sleep 1 ms
+ }
+
+ // D3 State, OFF
+ // NOTE: This is only possible if you only enable 1
+ // slot as both slot share the same clock and
+ // etc.
+ Method(_PS3) {
+ Store(One, SDRS)
+ Store(Zero, SDCE)
+ }
+
+ // Current Power State
+ Method(_PSC) {
+ if (LOr(NAnd(U0RS, One), LEqual(U0CE, Zero))) {
+ Return (3)
+ }
+ Return (0)
+ }
+ }
+ Device(\_SB.GP01) {
+ Name(_HID, "APMC0D14")
+ Name(_DDN, "GP01")
+ Name(_UID, "GP01")
+ Name(_STR, Unicode("GFC GPIO Device Port"))
+ Name(_CID, "GP01")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1701C000, 0x1000)
+ })
+ } //GP01 Device
+ } //AHBC
+////////////////////////////////////////////////////////////////////////////////
+// DesignWare I2C
+ Device (I2C0) {
+ // Serial IO I2C0 Controller
+ Name (_HID, "APMC0D0F")
+ Name (_CID, "APMC0D0F")
+ Name (_UID, 1)
+ Name (_ADR, 0x00150001)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x10512000, 0x10000,)
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x64 }
+ })
+ OperationRegion(\SMEM, SystemMemory, 0x1051E008, 4)
+ Field(\SMEM, DWordAcc, NoLock, Preserve) {
+ CLK0, 2,
+ }
+ Method(SPD, 0, NotSerialized) {
+ // initial clock value
+ Store(0xf4240, CLK0)
+ }
+ Method(_STA, 0, NotSerialized) {
+ Return (0x0)
+ }
+ } //I2C0 -- DesignWare
+////////////////////////////////////////////////////////////////////////////////
+// I2C1 VRM Bus
+
+ Device(\_SB.I2CS) {
+ //Device Identification Objects
+ Name(_HID, "I2CS0001")
+ Name(_DDN, "I2CS")
+ Name(_UID, "I2CS")
+ Name(_STR, Unicode("SLIMpro IIC1 Serial Bus"))
+
+//==============================================================================
+ //PMD+L3C VRM connection resource
+ Name(PCCG, ResourceTemplate() {
+ I2CSerialBus(
+ 0x10, //Slave Address(_ADR)
+ ControllerInitiated, //Slave Mode (_SLV)
+ 1000, //Connection speed in Hz (_SPE)
+ AddressingMode7Bit, //(_MOD)
+ "I2CS", //Controller
+ 0,
+ ResourceConsumer,
+ PCVR
+ )
+ }) //PCCG
+
+ //VRM Info Common to PMD+L3C
+ Device(PCPV) {
+ //Device Identification Objects
+ Name(_HID, "PCPV0000")
+ Name(_DDN, "PCCG")
+ Name(_UID, "PCCG")
+ Name(_STR, Unicode("APM88xxxx PMD+L3C VRM"))
+
+ //Resources used
+ Method(_CRS) {
+ Return (PCCG)
+ }
+ Method(_PRS) {
+ Return (PCCG)
+ }
+
+ //VRM Device Register Locations
+ Name(POWR, 0x36)
+ Name(CURR, 0x38)
+ Name(VOLT, 0x40)
+
+ } //PCPV
+
+//==============================================================================
+ //SOC VRM Connection resource
+ Name(SCCG, ResourceTemplate() {
+ I2CSerialBus(
+ 0x10, //Slave Address(_ADR)
+ ControllerInitiated, //Slave Mode (_SLV)
+ 1000, //Connection speed in Hz (_SPE)
+ AddressingMode7Bit, //(_MOD)
+ "I2CS", //Controller
+ 0,
+ ResourceConsumer,
+ SCVR
+ )
+ }) //SCCG
+
+ //VRM Info for SOC domain
+ Device(SOCV) {
+ //Device Identification Objects
+ Name(_HID, "SOCV0000")
+ Name(_DDN, "SCCG")
+ Name(_UID, "SCCG")
+ Name(_STR, Unicode("APM88xxxx SOC VRM"))
+
+ //Resources used
+ Method(_CRS) {
+ Return (SCCG)
+ }
+ Method(_PRS) {
+ Return (SCCG)
+ }
+
+ //VRM Device Register Locations
+ Name(POWR, 0x36)
+ Name(CURR, 0x38)
+ Name(VOLT, 0x40)
+ } //SOCV
+
+
+ } //I2C1
+
+///////////////////////////////////////////////////////////////////////////////
+// SATA Devices
+ Device(\_SB.SAT0) {
+ Name(_HID, "APMC0D00") // Device Identification Objects
+ Name(_UID, 1)
+ Name(_STR, Unicode("X-Gene SATA"))
+ Method(_STA, 0, NotSerialized)
+ {
+ Return (0x0)
+ }
+ Name(_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x1A000000, 0x1000)
+ Memory32Fixed (ReadWrite, 0x1F210000, 0x1000)
+ Memory32Fixed (ReadWrite, 0x1F21D000, 0x1000)
+ Memory32Fixed (ReadWrite, 0x1F21E000, 0x1000)
+ Memory32Fixed (ReadWrite, 0x1f217000, 0x1000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0xA6}
+ })
+ } //SAT0
+ Device(\_SB.SAT1) {
+ Name(_HID, "APMC0D0D") // Device Identification Objects
+ Name(_UID, 2)
+ Name(_STR, Unicode("X-Gene SATA"))
+ Method(_STA, 0, NotSerialized)
+ {
+ Return (0x1)
+ }
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x1A400000, 0x1000)
+ Memory32Fixed (ReadWrite, 0x1F220000, 0x1000)
+ Memory32Fixed (ReadWrite, 0x1F22D000, 0x1000)
+ Memory32Fixed (ReadWrite, 0x1F22E000, 0x1000)
+ Memory32Fixed (ReadWrite, 0x1f227000, 0x1000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0xA7}
+ })
+ } //SAT1
+ Device(\_SB.SAT2) {
+ Name(_HID, "APMC0D09") // Device Identification Objects
+ Name(_UID, 3)
+ Name(_STR, Unicode("X-Gene SATA"))
+ Method(_STA, 0, NotSerialized)
+ {
+ Return (0x1)
+ }
+ Name(_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x1A800000, 0x1000)
+ Memory32Fixed (ReadWrite, 0x1F230000, 0x1000)
+ Memory32Fixed (ReadWrite, 0x1F23D000, 0x1000)
+ Memory32Fixed (ReadWrite, 0x1F23E000, 0x1000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0xA8}
+ })
+ } //SAT2
+
+///////////////////////////////////////////////////////////////////////////////
+// USB Devices
+ Device(\_SB.USB0) {
+ Name(_HID, "APMC0D03")
+ Name(_DDN, "USB0")
+ Name(_UID, "USB0")
+ Name(_STR, Unicode("X-Gene USB"))
+ Method(_STA, 0, NotSerialized)
+ {
+ Return (0x1)
+ }
+ Name(_CID, "PNP0D10")
+ Name(_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x19000000, 0x100000)
+ Memory32Fixed (ReadWrite, 0x1F280000, 0x10000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0xA9}
+ })
+ } //USB0
+ Device(\_SB.USB1) {
+ Name(_HID, "APMC0D03")
+ Name(_DDN, "USB1")
+ Name(_UID, "USB1")
+ Name(_STR, Unicode("X-Gene USB"))
+ Method(_STA, 0, NotSerialized)
+ {
+ Return (0x1)
+ }
+ Name(_CID, "PNP0D10")
+ Name(_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x19800000, 0x100000)
+ Memory32Fixed (ReadWrite, 0x1F290000, 0x10000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0xAA}
+ })
+ } //USB1
+
+///////////////////////////////////////////////////////////////////////////////
+// QM Device
+ Device(\_SB.QM03) {
+ Name(_HID, "APMC0D04") // Device Identification Objects
+ Name(_DDN, "QM03")
+ Name(_UID, "QM03")
+ Name(_STR, Unicode("QM Lite Device"))
+ Name(_CID, "APMC0D04")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x17030000, 0x10000, )
+ Memory32Fixed(ReadWrite, 0x10000000, 0x400000, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x60 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x5C }
+ })
+ OperationRegion(CLKQ, SystemMemory, 0x1703c008, 4)
+ Field(CLKQ, DWordAcc, NoLock, Preserve) {
+ CLKE, 2,
+ }
+ Method(_INI, 0, NotSerialized) {
+ Store(0x3, CLKE)
+ Stall(100)
+ }
+ Method(_DSM, 4, NotSerialized) {
+ Store (Package (8) {
+ "max_queues", "1024",
+ "devid", "3",
+ "slave_name", "CPU_QMTM3",
+ "slave_info", "3 0 1 32 1",
+ }, Local0)
+ DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
+ Return (Local0)
+ }
+ } // QM03
+
+ Device(\_SB.QM01) {
+ Name(_HID, "APMC0D04") // Device Identification Objects
+ Name(_DDN, "QM01")
+ Name(_UID, "QM01")
+ Name(_STR, Unicode("QM 1 Device"))
+ Name(_CID, "APMC0D04")
+ Method(_STA, 0, NotSerialized) {
+ Return (0x1)
+ }
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1f200000, 0x10000, )
+ Memory32Fixed(ReadWrite, 0x1b000000, 0x400000, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xe0 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc0 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc1 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc2 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc3 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc4 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc5 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc6 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc7 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc8 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xc9 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xca }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xcb }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xcc }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xcd }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xce }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xcf }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd0 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd1 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd2 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd3 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd4 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd5 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd6 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd7 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd8 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xd9 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xda }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xdb }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xdc }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xdd }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xde }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xdf }
+ })
+ OperationRegion(CLKQ, SystemMemory, 0x1f20c008, 4)
+ Field(CLKQ, DWordAcc, NoLock, Preserve) {
+ CLKE, 2,
+ }
+ Method(_INI, 0, NotSerialized) {
+ Store(0x3, CLKE)
+ Stall(100)
+ }
+ Method(_DSM, 4, NotSerialized) {
+ Store (Package (8) {
+ "max_queues", "1024",
+ "devid", "1",
+ "slave_name", "CPU_QMTM1",
+ "slave_info", "1 0 32 32 32",
+ }, Local0)
+ DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
+ Return (Local0)
+ }
+ } // QM01
+
+ Device(\_SB.QM00) {
+ Name(_HID, "APMC0D04") // Device Identification Objects
+ Name(_DDN, "QM00")
+ Name(_UID, "QM00")
+ Name(_STR, Unicode("QM 0 Device"))
+ Name(_CID, "APMC0D04")
+ Method(_STA, 0, NotSerialized) {
+ Return (0x1)
+ }
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1f600000, 0x10000, )
+ Memory32Fixed(ReadWrite, 0x18000000, 0x400000, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xA0 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x80 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x81 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x82 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x83 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x84 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x85 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x86 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x87 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x88 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x89 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x8a }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x8b }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x8c }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x8d }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x8e }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x8f }
+ })
+ OperationRegion(CLKQ, SystemMemory, 0x1f60c008, 4)
+ Field(CLKQ, DWordAcc, NoLock, Preserve) {
+ CLKE, 2,
+ }
+ Method(_INI, 0, NotSerialized) {
+ Store(0x3, CLKE)
+ Stall(100)
+ }
+ Method(_DSM, 4, NotSerialized) {
+ Store (Package (8) {
+ "max_queues", "1024",
+ "devid", "0",
+ "slave_name", "CPU_QMTM0",
+ "slave_info", "0 0 16 32 16",
+ }, Local0)
+ DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
+ Return (Local0)
+ }
+ } // QM00
+
+ Device(\_SB.QM02) {
+ Name(_HID, "APMC0D04") // Device Identification Objects
+ Name(_DDN, "QM02")
+ Name(_UID, "QM02")
+ Name(_STR, Unicode("QM 2 Device"))
+ Name(_CID, "APMC0D04")
+ Method(_STA, 0, NotSerialized) {
+ Return (0x1)
+ }
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1f700000, 0x10000, )
+ Memory32Fixed(ReadWrite, 0x1e000000, 0x400000, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xE1 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x90 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x91 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x92 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x93 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x94 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x95 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x96 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x97 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x98 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x99 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x9a }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x9b }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x9c }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x9d }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x9e }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x9f }
+ })
+ OperationRegion(CLKQ, SystemMemory, 0x1f70c008, 4)
+ Field(CLKQ, DWordAcc, NoLock, Preserve) {
+ CLKE, 2,
+ }
+ Method(_INI, 0, NotSerialized) {
+ Store(0x3, CLKE)
+ Stall(100)
+ }
+ Method(_DSM, 4, NotSerialized) {
+ Store (Package (8) {
+ "max_queues", "1024",
+ "devid", "2",
+ "slave_name", "CPU_QMTM2",
+ "slave_info", "2 16 16 48 16",
+ }, Local0)
+ DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
+ Return (Local0)
+ }
+ } //QM02
+///////////////////////////////////////////////////////////////////////////////
+//SOC PLL and ETH Divider Fields
+//Operation Region For Eth Speed Control
+ OperationRegion(\SOCP, SystemMemory, 0x17000120, 4)
+ Field(\SOCP, DWordAcc, NoLock, Preserve) {
+ CLKF, 9,
+ RSV1, 11,
+ CLOD, 2,
+ RSV2, 2,
+ CLKR, 3,
+ RSV3, 5
+ }
+///////////////////////////////////////////////////////////////////////////////
+// Ethernet Device
+// APMC0D05: For Open Source
+// APMC0D19: For APM's driver. When APM driver sync up with open source then
+// this ID will be changed to APMC0D05
+ Device(\_SB.ET08) {
+ Name(_HID, "APMC0D05") // Device Identification Objects
+ Name(_DDN, "ET08")
+ Name(_UID, "ET08")
+ Name(_STR, Unicode("Ethernet RGMII Device Node Open Source"))
+ Name(_CID, "APMC0D05")
+ Method(_STA, 0, NotSerialized) {
+ Return (0x1)
+ }
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x17020000, 0xd100, )
+ Memory32Fixed(ReadWrite, 0x17030000, 0x10000, )
+ Memory32Fixed(ReadWrite, 0x10000000, 0x400000, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x5c }
+ })
+
+ OperationRegion(ETHD, SystemMemory, 0x17000238, 4)
+ Field(ETHD, DWordAcc, NoLock, Preserve) {
+ NDIV, 9,
+ }
+ Method(S10, 0, NotSerialized) {
+ // 10Mbps requires 2.5MHz clock
+ // SOC DIV 2 = REF * (CLKF/((CLKR+1) * (CLKD+1)))
+ // NDIV = (SOC DIV 2)/2500000
+ Store(Divide(Divide(Multiply(100000000, Divide(CLKF, Multiply(Add(CLKR, One), Add(CLOD, One)))), 2), 2500000), NDIV)
+ }
+ Method(S100, 0, NotSerialized) {
+ // 100Mbps requires 25MHz clock
+ // SOC DIV 2 = REF * (CLKF/((CLKR+1) * (CLKD+1)))
+ // 100Mbps = (SOC DIV 2)/25000000
+ Store(Divide(Divide(Multiply(100000000, Divide(CLKF, Multiply(Add(CLKR, One), Add(CLOD, One)))), 2), 25000000), NDIV)
+ }
+ Method(S1G, 0, NotSerialized) {
+ // 1Gbps requires 125MHz clock
+ // SOC DIV 2 = REF * (CLKF/((CLKR+1) * (CLKD+1)))
+ // NDIV = (SOC DIV 2)/125000000
+ Store(Divide(Divide(Multiply(100000000, Divide(CLKF, Multiply(Add(CLKR, One), Add(CLOD, One)))), 2), 125000000), NDIV)
+ }
+ OperationRegion(CLKQ, SystemMemory, 0x1702c008, 4)
+ Field(CLKQ, DWordAcc, NoLock, Preserve) {
+ CLKE, 2,
+ }
+ Method(_INI, 0, NotSerialized) {
+ Store(0x3, CLKE)
+ Stall(100)
+ }
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package (2) {"mac-address", Package (6) {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}},
+ Package (2) {"phy-channel", 3},
+ Package (2) {"phy-mode", "rgmii"},
+ Package (2) {"max-transfer-unit", 0x5dc}, // MTU of 1500
+ Package (2) {"max-speed", 0x3e8}, // 1000 Mbps
+ }
+ })
+ }
+
+
+ Device(\_SB.ET8) {
+ Name(_HID, "APMC0D19") // Device Identification Objects
+ Name(_DDN, "ET08")
+ Name(_UID, "ET08")
+ Name(_STR, Unicode("Ethernet RGMII Device for APM kernel"))
+ Name(_CID, "APMC0D19")
+ Method(_STA, 0, NotSerialized) {
+ Return (0x1)
+ }
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x17020000, 0xd100, )
+ Memory32Fixed(ReadWrite, 0x17020000, 0x10000, )
+ Memory32Fixed(ReadWrite, 0x17020000, 0x10000, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x58 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x59 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x5a }
+ })
+
+ OperationRegion(ETHD, SystemMemory, 0x17000238, 4)
+ Field(ETHD, DWordAcc, NoLock, Preserve) {
+ NDIV, 9,
+ }
+ Method(S10, 0, NotSerialized) {
+ // 10Mbps requires 2.5MHz clock
+ // SOC DIV 2 = REF * (CLKF/((CLKR+1) * (CLKD+1)))
+ // NDIV = (SOC DIV 2)/2500000
+ Store(Divide(Divide(Multiply(100000000, Divide(CLKF, Multiply(Add(CLKR, One), Add(CLOD, One)))), 2), 2500000), NDIV)
+ }
+ Method(S100, 0, NotSerialized) {
+ // 100Mbps requires 25MHz clock
+ // SOC DIV 2 = REF * (CLKF/((CLKR+1) * (CLKD+1)))
+ // 100Mbps = (SOC DIV 2)/25000000
+ Store(Divide(Divide(Multiply(100000000, Divide(CLKF, Multiply(Add(CLKR, One), Add(CLOD, One)))), 2), 25000000), NDIV)
+ }
+ Method(S1G, 0, NotSerialized) {
+ // 1Gbps requires 125MHz clock
+ // SOC DIV 2 = REF * (CLKF/((CLKR+1) * (CLKD+1)))
+ // NDIV = (SOC DIV 2)/125000000
+ Store(Divide(Divide(Multiply(100000000, Divide(CLKF, Multiply(Add(CLKR, One), Add(CLOD, One)))), 2), 125000000), NDIV)
+ }
+ OperationRegion(CLKQ, SystemMemory, 0x1702c008, 4)
+ Field(CLKQ, DWordAcc, NoLock, Preserve) {
+ CLKE, 2,
+ }
+ Method(_INI, 0, NotSerialized) {
+ Store(0x3, CLKE)
+ Stall(100)
+ }
+ Method(_DSM, 4, NotSerialized) {
+ Store (Package (14) {
+ "devid", "8",
+ "slave_name", "RGMII",
+ "slave_info", "3 0 4 32 4",
+ "max-frame-size", "9018",
+ "phyid", "3",
+ "phy-mode", "rgmii",
+ "local-mac-address", "00:00:00:00:00:00"
+ }, Local0)
+ DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
+ Return (Local0)
+ }
+ }
+
+ Device(\_SB.ET00) {
+ Name(_HID, "APMC0D19") // Device Identification Objects
+ Name(_DDN, "ET00")
+ Name(_UID, "ET00")
+ Name(_STR, Unicode("Ethernet SATA-SGMII Device"))
+ Name(_CID, "APMC0D19")
+ Method(_STA, 0, NotSerialized) {
+ Return (0x1)
+ }
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1f210000, 0x30, )
+ Memory32Fixed(ReadWrite, 0x1f210000, 0x10000, )
+ Memory32Fixed(ReadWrite, 0x17020000, 0x10000, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xac }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xad }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xb0 }
+ })
+ OperationRegion(CLKQ, SystemMemory, 0x1f21c008, 4)
+ Field(CLKQ, DWordAcc, NoLock, Preserve) {
+ CLKE, 4,
+ }
+ Method(_INI, 0, NotSerialized) {
+ Store(0xf, CLKE)
+ Stall(100)
+ }
+ Method(_DSM, 4, NotSerialized) {
+ Store (Package (14) {
+ "devid", "0",
+ "slave_name", "SGMII0",
+ "slave_info", "1 0 8 32 8",
+ "max-frame-size", "9018",
+ "phyid", "30",
+ "phy-mode", "sgmii",
+ "local-mac-address", "00:00:00:00:00:00"
+ }, Local0)
+ DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
+ Return (Local0)
+ }
+ }
+
+ Device(\_SB.ET01) {
+ Name(_HID, "APMC0D19") // Device Identification Objects
+ Name(_DDN, "ET01")
+ Name(_UID, "ET01")
+ Name(_STR, Unicode("Ethernet SATA-SGMII Device"))
+ Name(_CID, "APMC0D19")
+ Method(_STA, 0, NotSerialized) {
+ Return (0x1)
+ }
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1f210030, 0x30, )
+ Memory32Fixed(ReadWrite, 0x1f210000, 0x10000, )
+ Memory32Fixed(ReadWrite, 0x17020000, 0x10000, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xac }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xad }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0xb0 }
+ })
+ OperationRegion(CLKQ, SystemMemory, 0x1f21c008, 4)
+ Field(CLKQ, DWordAcc, NoLock, Preserve) {
+ CLKE, 4,
+ }
+ Method(_INI, 0, NotSerialized) {
+ Store(0xf, CLKE)
+ Stall(100)
+ }
+ Method(_DSM, 4, NotSerialized) {
+ Store (Package (14) {
+ "devid", "1",
+ "slave_name", "SGMII1",
+ "slave_info", "1 8 8 40 8",
+ "max-frame-size", "9018",
+ "phyid", "30",
+ "phy-mode", "sgmii",
+ "local-mac-address", "00:00:00:00:00:00"
+ }, Local0)
+ DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
+ Return (Local0)
+ }
+ }
+
+ Device(\_SB.ET04) {
+ Name(_HID, "APMC0D19") // Device Identification Objects
+ Name(_DDN, "ET04")
+ Name(_UID, "ET04")
+ Name(_STR, Unicode("Ethernet 10Gb Device"))
+ Name(_CID, "APMC0D19")
+ Method(_STA, 0, NotSerialized) {
+ Return (0x1)
+ }
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1f610000, 0x30, )
+ Memory32Fixed(ReadWrite, 0x1f610000, 0x10000, )
+ Memory32Fixed(ReadWrite, 0x17020000, 0x10000, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x70 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x71 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x72 }
+ })
+ OperationRegion(CLKQ, SystemMemory, 0x1f61c008, 4)
+ Field(CLKQ, DWordAcc, NoLock, Preserve) {
+ CLKE, 2,
+ }
+ Method(_INI, 0, NotSerialized) {
+ Store(0x3, CLKE)
+ Stall(100)
+ }
+ Method(_DSM, 4, NotSerialized) {
+ Store (Package (14) {
+ "devid", "4",
+ "slave_name", "SXGMII0",
+ "slave_info", "0 0 8 32 8",
+ "max-frame-size", "9018",
+ "phyid", "1",
+ "phy-mode", "xgmii",
+ "local-mac-address", "00:00:00:00:00:00"
+ }, Local0)
+ DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
+ Return (Local0)
+ }
+ }
+
+ Device(\_SB.ET05) {
+ Name(_HID, "APMC0D05") // Device Identification Objects
+ Name(_DDN, "ET05")
+ Name(_UID, "ET05")
+ Name(_STR, Unicode("Ethernet 10Gb Device"))
+ Name(_CID, "APMC0D05")
+ Method(_STA, 0, NotSerialized) {
+ Return (0x0)
+ }
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1f620000, 0x30, )
+ Memory32Fixed(ReadWrite, 0x1f620000, 0x10000, )
+ Memory32Fixed(ReadWrite, 0x17020000, 0x10000, )
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x73 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x74 }
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { 0x75 }
+ })
+ OperationRegion(CLKQ, SystemMemory, 0x1f61c008, 4)
+ Field(CLKQ, DWordAcc, NoLock, Preserve) {
+ CLKE, 2,
+ }
+ Method(_INI, 0, NotSerialized) {
+ Store(0x3, CLKE)
+ Stall(100)
+ }
+ Method(_DSM, 4, NotSerialized) {
+ Store (Package (14) {
+ "devid", "5",
+ "slave_name", "SXGMII1",
+ "slave_info", "0 0 8 32 8",
+ "max-frame-size", "9018",
+ "phyid", "1",
+ "phy-mode", "xgmii",
+ "local-mac-address", "00:00:00:00:00:00"
+ }, Local0)
+ DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
+ Return (Local0)
+ }
+ }
+///////////////////////////////////////////////////////////////////////////////
+//PCIe0
+ Device(\_SB.PCI0) {
+ //
+ // Hardware ID must be PNP0A08, which maps to a PCIe root complex.
+ // Section 6.1.5
+ //
+
+ Name(_HID,"PNP0A08")
+
+ //
+ // Optionally, include a compatible ID of PNP0A03, which maps to a PCI
+ // root complex for use with pre-PCIe operating systems.
+ // Section 6.1.2
+ //
+
+ Name(_CID,"PNP0A03")
+
+ //
+ // Declare the segment number of this root complex. Most systems only
+ // have one segment, which is numbered 0.
+ // Section 6.5.6
+ //
+
+ Name(_SEG, 0)
+
+ //
+ // Declare the base bus number, which is the bus number of the root
+ // bus in this root complex. This is usually 0, but need not be.
+ // For root complexes supporting multiple root busses, this should
+ // be the lowest numbered root bus.
+ // Section 6.5.5
+ //
+
+ Name(_BBN, 0)
+
+ //
+ // The _UID value provides a way of uniquely identifying a device
+ // in the case where more than one instance of a specific device
+ // is implemented with the same _HID/_CID. For systems with a
+ // single root complex, this is usually just 0. For systems with
+ // multiple root complexes, this should be different for each
+ // root complex.
+ // Section 6.1.12
+ //
+
+ Name(_UID, "PCI0")
+ Name(_STR, Unicode("PCIe 0 Device"))
+
+ //
+ // Declare the PCI Routing Table.
+ // This defines SPI mappings of the four line-based interrupts
+ // associated with the root complex and hierarchy below it.
+ // Section 6.2.12
+ //
+
+ Name(_PRT, Package() {
+
+ //
+ // Routing for device 0, all functions.
+ // Note: ARM doesn't support LNK nodes, so the third param
+ // is 0 and the fourth param is the SPI number of the interrupt
+ // line. In this example, the A/B/C/D interrupts are wired to
+ // SPI lines 100/101/102/103 respectively.
+ //
+
+ Package() {0x0000FFFF, 0, 0, 226},
+ Package() {0x0000FFFF, 1, 0, 227},
+ Package() {0x0000FFFF, 2, 0, 228},
+ Package() {0x0000FFFF, 3, 0, 229},
+ })
+
+ //
+ // Declare the resources assigned to this root complex.
+ // Section 6.2.2
+ //
+ Method (_CBA, 0, Serialized) {
+ Return (0xE0D0000000)
+ }
+ Method (_CRS, 0, Serialized) {
+
+ //
+ // Declare a ResourceTemplate buffer to return the resource
+ // requirements from _CRS.
+ // Section 19.5.109
+ //
+
+ Name (RBUF, ResourceTemplate () {
+
+ //
+ // Declare the range of bus numbers assigned to this root
+ // complex. In this example, the minimum bus number will be
+ // 0, the maximum bus number will be 0xFF, supporting
+ // 256 busses total.
+ // Section 19.5.141
+ //
+
+ WordBusNumber (
+ ResourceProducer,
+ MinFixed, // IsMinFixed
+ MaxFixed, // IsMaxFixed
+ PosDecode, // Decode
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256) // RangeLength - Number of Busses
+
+ //
+ // Declare the memory range to be used for BAR memory
+ // windows. This declares a 4GB region starting at
+ // 0x4000000000.
+ // Section 19.5.80
+ //
+ Memory32Fixed(ReadWrite, 0x1F2B0000, 0x10000, )
+
+ QWordIO(
+ ResourceConsumer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0000000000000000,
+ 0x0000000010000000,
+ 0x000000001000FFFF,
+ 0x000000E000000000,
+ 0x0000000000010000
+ )
+ QWordMemory(
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0000000000000000,
+ 0x0000000030000000,
+ 0x0000000030FFFFFF,
+ 0x000000E000000000,
+ 0x0000000001000000
+ )
+ QWordMemory(
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0000000000000000,
+ 0x000000e100000000,
+ 0x000000e13FFFFFFF,
+ 0x0000000000000000,
+ 0x0000000040000000
+ )
+ })
+
+ Return (RBUF)
+ }
+
+ //
+ // Declare an _OSC (OS Control Handoff) method which takes 4 arguments.
+ //
+ // Argments:
+ // Arg0 A Buffer containing a UUID
+ // Arg1 An Integer containing a Revision ID of the buffer format
+ // Arg2 An Integer containing a count of entries in Arg3
+ // Arg3 A Buffer containing a list of DWORD capabilities
+ // Return Value:
+ // A Buffer containing a list of capabilities
+ // See the APCI spec, Section 6.2.10,
+ // and the PCI FW spec, Section 4.5.
+ //
+ // The following is an example, and may need modification for
+ // specific implementations.
+ //
+
+ Name(SUPP,0) // PCI _OSC Support Field value
+ Name(CTRL,0) // PCI _OSC Control Field value
+ Method(_OSC, 4) {
+
+ //
+ // Look for the PCI Host Bridge Interface UUID.
+ // Section 6.2.10.3
+ //
+
+ //
+ // Create DWord-adressable fields from the Capabilities Buffer
+ // Create CDW1 outside the test as it's used in the else clause.
+ //
+
+ CreateDWordField(Arg3,0,CDW1)
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ CreateDWordField(Arg3,4,CDW2)
+ CreateDWordField(Arg3,8,CDW3)
+
+ //
+ // Save Capabilities DWord 2 & 3
+ //
+
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports:
+ // ASPM
+ // Clock PM
+ // MSI/MSI-X
+ //
+
+ // Storm, no hotplug, but still return bit 0 set
+ // because win won't be happy.
+ And(CTRL,0x1D,CTRL)
+
+ //If(LNotEqual(And(SUPP, 0x16), 0x16)) {
+
+ //
+ // Mask bit 0 (and undefined bits)
+ //
+
+ // And(CTRL,0x1E,CTRL)
+ //}
+
+ //
+ // Always allow native PME, AER (no dependencies).
+ // Never allow SHPC (no SHPC controller in this system).
+ //
+
+ And(CTRL,0x1D,CTRL)
+
+ //
+ // Check for unknown revision.
+ //
+
+ If(LNotEqual(Arg1,One)) {
+ Or(CDW1,0x08,CDW1)
+ }
+
+ //
+ // Check if capabilities bits were masked.
+ //
+
+ If(LNotEqual(CDW3,CTRL)) {
+ Or(CDW1,0x10,CDW1)
+ }
+
+ //
+ // Update DWORD3 in the buffer.
+ //
+
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+
+ //
+ // Unrecognized UUID
+ //
+
+ Or(CDW1,4,CDW1)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ //
+ // Declare a _DSM method for various functions called by the OS.
+ // See the APCI spec, Section 9.14.1,
+ // and the PCI FW spec, Section 4.6.
+ // See also:
+ // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc
+ //
+
+ Method(_DSM, 0x4, Serialized) {
+
+ //
+ // Match against the _DSM PCI GUID.
+ //
+
+ If(LEqual(Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
+
+ switch(ToInteger(Arg2))
+ {
+ //
+ // Function 0: Return supported functions as a bitfield
+ // with one bit for each supported function.
+ // Bit 0 must always be set, as that represents
+ // function 0 (which is what is being called here).
+ // Support for different functions may depend on
+ // the revision ID of the interface, passed as Arg1.
+ //
+
+ case(0) {
+
+ //
+ // Functions 0-7 are supported.
+ //
+
+ return (Buffer() {0x01})
+ }
+
+
+ }
+ }
+
+ //
+ // If not one of the function identifiers we recognize, then return a buffer
+ // with bit 0 set to 0 indicating no functions supported.
+ //
+
+ return(Buffer(){0})
+ }
+
+ //
+ // Root Port 0 Device within the Root Complex.
+ //
+
+ Device(RP0) {
+
+ //
+ // Device 0, Function 0.
+ //
+
+ Name(_ADR, 0x00000000)
+
+ //
+ // Power resources required for D0.
+ //
+
+ Name(_PR0, Package() {SCVR})
+
+ //
+ // Power resources required for D3Hot.
+ //
+
+ Name(_PR3, Package(){SCVR})
+ }
+ } // PCI0
+
+///////////////////////////////////////////////////////////////////////////////
+// MSI
+ Device(\_SB.MSIX) {
+ Name(_HID, "APMC0D0E") // Device Identification Objects
+ Name(_UID, 0)
+ Name(_STR, Unicode("X-Gene MSI/MSIX"))
+ Method(_STA, 0, NotSerialized)
+ {
+ Return (One)
+ }
+ Name(_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x79000000, 0x900000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x30}
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x31}
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x32}
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x33}
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x34}
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x35}
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x36}
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x37}
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x38}
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x39}
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x3A}
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x3B}
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x3C}
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x3D}
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x3E}
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x3F}
+ })
+ Method(_DSM, 4, NotSerialized) {
+ Store (Package (2) {
+ "msi-available-ranges", "0x0 0x1000",
+ }, Local0)
+ DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
+ Return (Local0)
+ }
+ }
+
+///////////////////////////////////////////////////////////////////////////////
+// PktDMA
+ Device(\_SB.PDMA) {
+ Name(_HID, "APMC0D16") // Device Identification Objects
+ Name(_UID, 0)
+ Name(_STR, Unicode("X-Gene PktDMA"))
+ Method(_STA, 0, NotSerialized) {
+ Return (One)
+ }
+ Name(_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x1f270000, 0x10000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0xA3}
+ })
+ OperationRegion(RSTQ, SystemMemory, 0x1f27c000, 4)
+ Field(RSTQ, DWordAcc, NoLock, Preserve) {
+ RSTE, 2,
+ }
+ OperationRegion(CLKQ, SystemMemory, 0x1f27c008, 4)
+ Field(CLKQ, DWordAcc, NoLock, Preserve) {
+ CLKE, 2,
+ }
+ Method(_INI, 0, NotSerialized) {
+ Store(0x3, RSTE)
+ Stall(100)
+ Store(0x0, RSTE)
+ Stall(100)
+ Store(0x3, CLKE)
+ Stall(100)
+ }
+ }
+
+///////////////////////////////////////////////////////////////////////////////
+// Pkt
+ Device(\_SB.PKA) {
+ Name(_HID, "APMC0D17") // Device Identification Objects
+ Name(_UID, 0)
+ Name(_STR, Unicode("X-Gene Pka"))
+ Method(_STA, 0, NotSerialized) {
+ Return (One)
+ }
+ Name(_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x10524000, 0x4000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x63}
+ })
+ OperationRegion(RSTQ, SystemMemory, 0x1700000c, 4)
+ Field(RSTQ, DWordAcc, NoLock, Preserve) {
+ RSV1, 4,
+ RSTE, 1,
+ }
+ OperationRegion(CLKQ, SystemMemory, 0x17000010, 4)
+ Field(CLKQ, DWordAcc, NoLock, Preserve) {
+ RSV2, 4,
+ CLKE, 1,
+ }
+ Method(_INI, 0, NotSerialized) {
+ If (LNot(CLKE)) {
+ Store(0x1, RSTE)
+ Stall(100)
+ Store(0x0, RSTE)
+ Stall(100)
+ Store(0x1, CLKE)
+ Stall(100)
+ }
+ }
+ }
+
+///////////////////////////////////////////////////////////////////////////////
+// Trng
+ Device(\_SB.TRNG) {
+ Name(_HID, "APMC0D18") // Device Identification Objects
+ Name(_UID, 0)
+ Name(_STR, Unicode("X-Gene TRNG"))
+ Method(_STA, 0, NotSerialized) {
+ Return (One)
+ }
+ Name(_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x10520000, 0x4000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x61}
+ })
+ OperationRegion(RSTQ, SystemMemory, 0x1700000c, 4)
+ Field(RSTQ, DWordAcc, NoLock, Preserve) {
+ RSV1, 4,
+ RSTE, 1,
+ }
+ OperationRegion(CLKQ, SystemMemory, 0x17000010, 4)
+ Field(CLKQ, DWordAcc, NoLock, Preserve) {
+ RSV2, 4,
+ CLKE, 1,
+ }
+ Method(_INI, 0, NotSerialized) {
+ If (LNot(CLKE)) {
+ Store(0x1, RSTE)
+ Stall(100)
+ Store(0x0, RSTE)
+ Stall(100)
+ Store(0x1, CLKE)
+ Stall(100)
+ }
+ }
+ }
+
+///////////////////////////////////////////////////////////////////////////////
+}//DSDT
diff --git a/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Facp.asl b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Facp.asl
new file mode 100644
index 0000000..06035bd
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Facp.asl
@@ -0,0 +1,179 @@
+/**
+ * Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+ *
+ * This program and the accompanying materials are licensed and made
+ * available under the terms and conditions of the BSD License which
+ * accompanies this distribution. The full text of the license may be
+ * found at * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ * [FACP] ACPI Table
+ *
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ **/
+
+[0004] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[0004] Table Length : 0000010C
+[0001] Revision : 05
+[0001] Checksum : 18
+[0006] Oem ID : "APM "
+[0008] Oem Table ID : "XGENE "
+[0004] Oem Revision : 00000003
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20111123
+
+[0004] FACS Address : 00000000
+[0004] DSDT Address : FFFFFFFF
+[0001] Model : 00
+[0001] PM Profile : 00 [Unspecified]
+[0002] SCI Interrupt : 0000
+[0004] SMI Command Port : 00000000
+[0001] ACPI Enable Value : 00
+[0001] ACPI Disable Value : 00
+[0001] S4BIOS Command : 00
+[0001] P-State Control : 00
+[0004] PM1A Event Block Address : 00000000
+[0004] PM1B Event Block Address : 00000000
+[0004] PM1A Control Block Address : 00000000
+[0004] PM1B Control Block Address : 00000000
+[0004] PM2 Control Block Address : 00000000
+[0004] PM Timer Block Address : 00000000
+[0004] GPE0 Block Address : 00000000
+[0004] GPE1 Block Address : 00000000
+[0001] PM1 Event Block Length : 00
+[0001] PM1 Control Block Length : 00
+[0001] PM2 Control Block Length : 00
+[0001] PM Timer Block Length : 00
+[0001] GPE0 Block Length : 00
+[0001] GPE1 Block Length : 00
+[0001] GPE1 Base Offset : 00
+[0001] _CST Support : 00
+[0002] C2 Latency : 0000
+[0002] C3 Latency : 0000
+[0002] CPU Cache Size : 0000
+[0002] Cache Flush Stride : 0000
+[0001] Duty Cycle Offset : 00
+[0001] Duty Cycle Width : 00
+[0001] RTC Day Alarm Index : 00
+[0001] RTC Month Alarm Index : 00
+[0001] RTC Century Index : 00
+[0002] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[0001] Reserved : 00
+[0004] Flags (decoded below) : 00100000
+ WBINVD instruction is operational (V1) : 0
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 0
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 0
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 0
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 0
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 0
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 1
+ Low Power S0 Idle (V5) : 0
+
+[0012] Reset Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000000
+
+[0001] Value to cause reset : 00
+[0002] ARM_BOOT_ARCH (decoded below) : 0000
+ Use PSCI 0.2+ : 0
+ PSCI Use HVC : 0
+[0001] FADT Minor Revision : 01
+[0008] FACS Address : 0000000000000000
+[0008] DSDT Address : 0000000000000010
+[0012] PM1A Event Block : [Generic Address Structure]
+[0001] Space ID : 00 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Word Access:16]
+[0008] Address : 0000000000000000
+
+[0012] PM1B Event Block : [Generic Address Structure]
+[0001] Space ID : 00 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0012] PM1A Control Block : [Generic Address Structure]
+[0001] Space ID : 00 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Word Access:16]
+[0008] Address : 0000000000000000
+
+[0012] PM1B Control Block : [Generic Address Structure]
+[0001] Space ID : 00 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0012] PM2 Control Block : [Generic Address Structure]
+[0001] Space ID : 00 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0012] PM Timer Block : [Generic Address Structure]
+[0001] Space ID : 00 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [DWord Access:32]
+[0008] Address : 0000000000000000
+
+[0012] GPE0 Block : [Generic Address Structure]
+[0001] Space ID : 00 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Byte Access:8]
+[0008] Address : 0000000000000000
+
+[0012] GPE1 Block : [Generic Address Structure]
+[0001] Space ID : 00 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+
+[0012] Sleep Control Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemIO]
+[0001] Bit Width : 20
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [Byte Access:8]
+[0008] Address : 0000000010558008
+
+[0012] Sleep Status Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemIO]
+[0001] Bit Width : 20
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 04 [Byte Access:8]
+[0008] Address : 0000000010558000
+
diff --git a/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Facs.asl b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Facs.asl
new file mode 100644
index 0000000..a21f207
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Facs.asl
@@ -0,0 +1,28 @@
+/**
+ * Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ * [FACS] ACPI Table
+ *
+ **/
+
+[0004] Signature : "FACS"
+[0004] Length : 00000040
+[0004] Hardware Signature : 00000000
+[0004] 32 Firmware Waking Vector : 00000000
+[0004] Global Lock : 00000000
+[0004] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[0008] 64 Firmware Waking Vector : 0000000000000000
+[0001] Version : 02
+[0003] Reserved : 000000
+[0004] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
diff --git a/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Gtdt.asl b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Gtdt.asl
new file mode 100644
index 0000000..6d3a7d0
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Gtdt.asl
@@ -0,0 +1,107 @@
+/**
+ * Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ * GTDT Table for X-Gene Processor
+ *
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ **/
+
+[0004] Signature : "GTDT" [Generic Timer Description Table]
+[0004] Table Length : 000000E0
+[0001] Revision : 02
+[0001] Checksum : B0
+[0006] Oem ID : "APM "
+[0008] Oem Table ID : "XGENE "
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20140424
+
+[0008] Counter Block Address : 0000000000000000
+[0004] Reserved : 00000000
+
+[0004] Secure EL1 Interrupt : 00000010
+[0004] EL1 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+ Always On : 0
+
+[0004] Non-Secure EL1 Interrupt : 0000001D
+[0004] NEL1 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+ Always On : 0
+
+[0004] Virtual Timer Interrupt : 0000001E
+[0004] VT Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+ Always On : 0
+
+[0004] Non-Secure EL2 Interrupt : 0000001F
+[0004] NEL2 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+ Always On : 0
+[0008] Counter Read Block Address : 0000000000000000
+
+[0004] Platform Timer Count : 00000002
+[0004] Platform Timer Offset : 00000060
+
+[0001] Subtable Type : 00 [GT Block]
+[0001] Length : 64
+[0002] Reserved : 0000
+[0008] GT Block Address : 0000000000000000
+[0004] GT Block Count : 00000002
+[0004] GT Block Offset : 00000014
+
+[0001] GT Frame Number : 00
+[0003] Reserved : 000000
+[0008] GTx Address : 0000000000000000
+[0008] GTx EL0 Address : 0000000000000000
+[0004] GTx Timer Interrupt : 00000000
+[0004] GTx Timer Flags (decoded below) : 00000001
+ Trigger Mode : 1
+ Polarity : 0
+[0004] GTx Virtual Timer Interrupt : 00000000
+[0004] GTx Virtual Timer Flags (decoded below) : 00000001
+ Trigger Mode : 1
+ Polarity : 0
+[0004] GTx Common Flags (decoded below) : 00000000
+ Secure : 0
+ Always On : 0
+
+[0001] GT Frame Number : 01
+[0003] Reserved : 000000
+[0008] GTx Address : 0000000000000000
+[0008] GTx EL0 Address : 0000000000000000
+[0004] GTx Timer Interrupt : 00000000
+[0004] GTx Timer Flags (decoded below) : 00000001
+ Trigger Mode : 1
+ Polarity : 0
+[0004] GTx Virtual Timer Interrupt : 00000000
+[0004] GTx Virtual Timer Flags (decoded below) : 00000001
+ Trigger Mode : 1
+ Polarity : 0
+[0004] GTx Common Flags (decoded below) : 00000000
+ Secure : 0
+ Always On : 0
+
+[0001] Subtable Type : 01 [SBSA Generic Watchdog]
+[0001] Length : 1C
+[0002] Reserved : 0000
+[0008] Refresh Frame Address : 0000000000000000
+[0008] Control Frame Address : 0000000000000000
+[0004] Timer Interrupt : 00000000
+[0004] Timer Flags (decoded below) : 00000001
+ Trigger Mode : 1
+ Polarity : 0
+ Secure : 0
diff --git a/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Mcfg.asl b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Mcfg.asl
new file mode 100644
index 0000000..86d66d3
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Mcfg.asl
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2014, AppliedMicro Corp. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ */
+
+[0004] Signature : "MCFG" [Memory Mapped Configuration table]
+[0004] Table Length : 0000003C
+[0001] Revision : 01
+[0001] Checksum : 96
+[0006] Oem ID : "APM "
+[0008] Oem Table ID : "XGENE "
+[0004] Oem Revision : 00000002
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0008] Reserved : 0000000000000000
+
+[0008] Base Address : 000000e0d0000000
+[0002] Segment Group Number : 0000
+[0001] Start Bus Number : 00
+[0001] End Bus Number : 00
+[0004] Reserved : 00000000
diff --git a/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Rsdp.asl b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Rsdp.asl
new file mode 100644
index 0000000..af7a226
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Rsdp.asl
@@ -0,0 +1,24 @@
+/**
+ * Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ * [RSDP] ACPI Table
+ *
+ **/
+
+[0008] Signature : "RSD PTR "
+[0001] Checksum : 43
+[0006] Oem ID : "APM "
+[0001] Revision : 02
+[0004] RSDT Address : 00000000
+[0004] Length : 00000024
+[0008] XSDT Address : 0000004003800024
+[0001] Extended Checksum : DC
+[0003] Reserved : 000000
diff --git a/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Spcr.asl b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Spcr.asl
new file mode 100644
index 0000000..711676c
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Spcr.asl
@@ -0,0 +1,46 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20131115-64 [Dec 9 2013]
+ * Copyright (c) 2000 - 2013 Intel Corporation
+ *
+ * Template for [SPCR] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+
+[0004] Signature : "SPCR" [Serial Port Console Redirection table]
+[0004] Table Length : 00000050
+[0001] Revision : 01
+[0001] Checksum : E3
+[0006] Oem ID : "APMC0D"
+[0008] Oem Table ID : "XGENESPC"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0001] Interface Type : 00
+[0003] Reserved : 000000
+
+[0012] Serial Port Register : [Generic Address Structure]
+[0001] Space ID : 00 [SystemMemory]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Undefined/Legacy]
+[0008] Address : 000000001c020000
+
+[0001] Interrupt Type : 00
+[0001] PCAT-compatible IRQ : 00
+[0004] Interrupt : 00000000
+[0001] Baud Rate : 07
+[0001] Parity : 00
+[0001] Stop Bits : 01
+[0001] Flow Control : 00
+[0001] Terminal Type : 00
+[0001] Reserved : 00
+[0002] PCI Device ID : FFFF
+[0002] PCI Vendor ID : FFFF
+[0001] PCI Bus : 00
+[0001] PCI Device : 00
+[0001] PCI Function : 00
+[0004] PCI Flags : 00000000
+[0001] PCI Segment : 00
+[0004] Reserved : 00000000
diff --git a/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Ssdt.asl b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Ssdt.asl
new file mode 100644
index 0000000..f5ce1d0
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Ssdt.asl
@@ -0,0 +1,21 @@
+/**
+ * Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ **/
+
+DefinitionBlock("Ssdt.aml", "SSDT", 2, "APM ", "XGENE ", 0x00000001)
+{
+ Method (MAIN, 0, NotSerialized)
+ {
+ Return (Zero)
+ }
+}
+
diff --git a/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Xsdt.asl b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Xsdt.asl
new file mode 100644
index 0000000..7214d4b
--- /dev/null
+++ b/Platforms/APM/XGene/AcpiTables/APMXGene-Mustang/Xsdt.asl
@@ -0,0 +1,29 @@
+/**
+ * Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ * [XSDT] ACPI Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ **/
+
+[0004] Signature : "XSDT" [Extended System Description Table]
+[0004] Table Length : 00000064
+[0001] Revision : 01
+[0001] Checksum : 8B
+[0006] Oem ID : "APM "
+[0008] Oem Table ID : "XGENE "
+[0004] Oem Revision : 00000002
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0008] ACPI Table Address 0 : 00000004003800060
+[0008] ACPI Table Address 1 : 0000000400380016C
+[0008] ACPI Table Address 2 : 000000040038001BC
diff --git a/Platforms/APM/XGene/Applications/AppPkg.dec b/Platforms/APM/XGene/Applications/AppPkg.dec
new file mode 100755
index 0000000..91e8b54
--- /dev/null
+++ b/Platforms/APM/XGene/Applications/AppPkg.dec
@@ -0,0 +1,31 @@
+##
+# Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+##
+
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = AppPkg
+ PACKAGE_GUID = B6C4E1A0-AA18-11E3-A5E2-0800200C9A66
+ PACKAGE_VERSION = 0.01
+
+
+[Guids]
+ gAppPkgTokenSpaceGuid = { 0xd85f7b40, 0xaa18, 0x11e3, { 0xa5, 0xe2, 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66 }}
+
+
+[PcdsFixedAtBuild]
+ gAppPkgTokenSpaceGuid.EepromAddrLen|2|UINT32|0
+ gAppPkgTokenSpaceGuid.EepromPageWriteBits|8|UINT32|1
+ gAppPkgTokenSpaceGuid.EepromAddr|0x52|UINT32|2
+ gAppPkgTokenSpaceGuid.FirmwareBlockDevicePath|L"VenHw(6C9CEEF0-A406-11E3-A5E2-0800200C9A66)"|VOID*|4
+ gAppPkgTokenSpaceGuid.FirmwareBlockDevicePathNext|L"VenHw(02118005-9DA7-443A-92D5-781F022AEDBB)"|VOID*|5
+
diff --git a/Platforms/APM/XGene/Applications/AppPkg.dsc b/Platforms/APM/XGene/Applications/AppPkg.dsc
new file mode 100755
index 0000000..4ab9a7a
--- /dev/null
+++ b/Platforms/APM/XGene/Applications/AppPkg.dsc
@@ -0,0 +1,145 @@
+##
+# Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+##
+
+[Defines]
+ PLATFORM_NAME = APMXGene-Mustang-Apps
+ PLATFORM_GUID = 0c74c420-a335-11e3-a5e2-0800200c9a66
+ PLATFORM_VERSION = 0.01
+ DSC_SPECIFICATION = 0x00010006
+ OUTPUT_DIRECTORY = Build/APMXGene-Mustang
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+
+#
+# Debug output control
+#
+ # DEBUG_ASSERT_ENABLED 0x01
+ # DEBUG_PRINT_ENABLED 0x02
+ # DEBUG_CODE_ENABLED 0x04
+ # CLEAR_MEMORY_ENABLED 0x08
+ # ASSERT_BREAKPOINT_ENABLED 0x10
+ # ASSERT_DEADLOOP_ENABLED 0x20
+!if $(TARGET) == RELEASE
+ DEFINE DEBUG_PROPERTY_MASK = 0x21
+ DEFINE DEBUG_ENABLE_OUTPUT = FALSE # Set to TRUE to enable debug output
+!else
+ DEFINE DEBUG_PROPERTY_MASK = 0x2f
+ DEFINE DEBUG_ENABLE_OUTPUT = TRUE # Set to TRUE to enable debug output
+!endif
+
+ DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x80000040 # Flags to control amount of debug output
+
+[BuildOptions]
+ GCC:*_*_AARCH64_ARCHCC_FLAGS = -mgeneral-regs-only -DARM_CPU_AARCH64 -DAPM_XGENE
+ GCC:*_*_AARCH64_PP_FLAGS = -DARM_CPU_AARCH64
+ GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/APMXGenePkg/Include -I$(WORKSPACE)/ArmPlatformPkg/APMXGenePkg/Modules/ArmPlatformPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/APMXGenePkg/Modules/EmbeddedPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/APMXGenePkg/Modules/MdePkg/Include
+
+[PcdsFeatureFlag]
+
+[PcdsFixedAtBuild]
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|$(DEBUG_PROPERTY_MASK)
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEVEL)
+ #
+ # ARM Architectual Timer Frequency
+ #
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000
+
+[LibraryClasses]
+ #
+ # Entry Point Libraries
+ #
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ #
+ # Common Libraries
+ #
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ !if $(DEBUG_ENABLE_OUTPUT)
+ DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+ !else ## DEBUG_ENABLE_OUTPUT
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ !endif ## DEBUG_ENABLE_OUTPUT
+
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+ PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ FileHandleLib|ShellPkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ SortLib|ShellPkg/Library/UefiSortLib/UefiSortLib.inf
+ PathLib|MdeModulePkg/Library/BasePathLib/BasePathLib.inf
+
+ CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ I2CLib|ArmPlatformPkg/APMXGenePkg/Library/I2CLib/I2CLib.inf
+ SlimproLib|ArmPlatformPkg/APMXGenePkg/Library/SlimproLib/SlimproLib.inf
+
+###################################################################################################
+#
+# Components Section - list of the modules and components that will be processed by compilation
+# tools and the EDK II tools to generate PE32/PE32+/Coff image files.
+#
+# Note: The EDK II DSC file is not used to specify how compiled binary images get placed
+# into firmware volume images. This section is just a list of modules to compile from
+# source into UEFI-compliant binaries.
+# It is the FDF file that contains information on combining binary files into firmware
+# volume images, whose concept is beyond UEFI and is described in PI specification.
+# Binary modules do not need to be listed in this section, as they should be
+# specified in the FDF file. For example: Shell binary (Shell_Full.efi), FAT binary (Fat.efi),
+# Logo (Logo.bmp), and etc.
+# There may also be modules listed in this section that are not required in the FDF file,
+# When a module listed here is excluded from FDF file, then UEFI-compliant binary will be
+# generated for it, but the binary will not be put into any firmware volume.
+#
+###################################################################################################
+
+[Components]
+
+#### Sample Applications.
+ ArmPlatformPkg/APMXGenePkg/Applications/UpgradeFirmware/UpgradeFirmware.inf # No LibC includes or functions.
+ ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+
+
+##############################################################################
+#
+# Specify whether we are running in an emulation environment, or not.
+# Define EMULATE if we are, else keep the DEFINE commented out.
+#
+# DEFINE EMULATE = 1
+
+##############################################################################
+#
+# Include Boilerplate text required for building with the Standard Libraries.
+#
+##############################################################################
+#!include StdLib/StdLib.inc
+#!include AppPkg/Applications/Sockets/Sockets.inc
diff --git a/Platforms/APM/XGene/Applications/UpgradeFirmware/Md5.c b/Platforms/APM/XGene/Applications/UpgradeFirmware/Md5.c
new file mode 100755
index 0000000..981dc67
--- /dev/null
+++ b/Platforms/APM/XGene/Applications/UpgradeFirmware/Md5.c
@@ -0,0 +1,350 @@
+/** @file
+ Implementation of MD5 algorithm.
+
+Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "Md5.h"
+
+CONST UINT32 Md5_Data[][2] = {
+ { 0, 1 },
+ { 1, 5 },
+ { 5, 3 },
+ { 0, 7 }
+};
+
+CONST UINT32 Md5_S[][4] = {
+ { 7, 22, 17, 12 },
+ { 5, 20, 14, 9 },
+ { 4, 23, 16 ,11 },
+ { 6, 21, 15, 10 },
+};
+
+CONST UINT32 Md5_T[] = {
+ 0xD76AA478, 0xE8C7B756, 0x242070DB, 0xC1BDCEEE,
+ 0xF57C0FAF, 0x4787C62A, 0xA8304613, 0xFD469501,
+ 0x698098D8, 0x8B44F7AF, 0xFFFF5BB1, 0x895CD7BE,
+ 0x6B901122, 0xFD987193, 0xA679438E, 0x49B40821,
+ 0xF61E2562, 0xC040B340, 0x265E5A51, 0xE9B6C7AA,
+ 0xD62F105D, 0x02441453, 0xD8A1E681, 0xE7D3FBC8,
+ 0x21E1CDE6, 0xC33707D6, 0xF4D50D87, 0x455A14ED,
+ 0xA9E3E905, 0xFCEFA3F8, 0x676F02D9, 0x8D2A4C8A,
+ 0xFFFA3942, 0x8771F681, 0x6D9D6122, 0xFDE5380C,
+ 0xA4BEEA44, 0x4BDECFA9, 0xF6BB4B60, 0xBEBFBC70,
+ 0x289B7EC6, 0xEAA127FA, 0xD4EF3085, 0x04881D05,
+ 0xD9D4D039, 0xE6DB99E5, 0x1FA27CF8, 0xC4AC5665,
+ 0xF4292244, 0x432AFF97, 0xAB9423A7, 0xFC93A039,
+ 0x655B59C3, 0x8F0CCC92, 0xFFEFF47D, 0x85845DD1,
+ 0x6FA87E4F, 0xFE2CE6E0, 0xA3014314, 0x4E0811A1,
+ 0xF7537E82, 0xBD3AF235, 0x2AD7D2BB, 0xEB86D391
+};
+
+CONST UINT8 Md5HashPadding[] =
+{
+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+//
+// ROTATE_LEFT rotates x left n bits.
+//
+#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32 - (n))))
+
+#define SA MedStates[Index2 & 3]
+#define SB MedStates[(Index2 + 1) & 3]
+#define SC MedStates[(Index2 + 2) & 3]
+#define SD MedStates[(Index2 + 3) & 3]
+
+/**
+ Tf1 is one basic MD5 transform function.
+
+ @param[in] A A 32-bit quantity.
+ @param[in] B A 32-bit quantity.
+ @param[in] C A 32-bit quantity.
+
+ @return Output was produced as a 32-bit quantity based on the
+ three 32-bit input quantity.
+**/
+UINT32
+Tf1 (
+ IN UINT32 A,
+ IN UINT32 B,
+ IN UINT32 C
+ )
+{
+ return (A & B) | (~A & C);
+}
+
+/**
+ Tf2 is one basic MD5 transform function.
+
+ @param[in] A A 32-bit quantity.
+ @param[in] B A 32-bit quantity.
+ @param[in] C A 32-bit quantity.
+
+ @return Output was produced as a 32-bit quantity based on the
+ three 32-bit input quantity.
+**/
+UINT32
+Tf2 (
+ IN UINT32 A,
+ IN UINT32 B,
+ IN UINT32 C
+ )
+{
+ return (A & C) | (B & ~C);
+}
+
+/**
+ Tf3 is one basic MD5 transform function.
+
+ @param[in] A A 32-bit quantity.
+ @param[in] B A 32-bit quantity.
+ @param[in] C A 32-bit quantity.
+
+ @return Output was produced as a 32-bit quantity based on the
+ three 32-bit input quantity.
+**/
+UINT32
+Tf3 (
+ IN UINT32 A,
+ IN UINT32 B,
+ IN UINT32 C
+ )
+{
+ return A ^ B ^ C;
+}
+
+/**
+ Tf4 is one basic MD5 transform function.
+
+ @param[in] A A 32-bit quantity.
+ @param[in] B A 32-bit quantity.
+ @param[in] C A 32-bit quantity.
+
+ @return Output was produced as a 32-bit quantity based on the
+ three 32-bit input quantity.
+**/
+UINT32
+Tf4 (
+ IN UINT32 A,
+ IN UINT32 B,
+ IN UINT32 C
+ )
+{
+ return B ^ (A | ~C);
+}
+
+typedef
+UINT32
+(*MD5_TRANSFORM_FUNC) (
+ IN UINT32 A,
+ IN UINT32 B,
+ IN UINT32 C
+ );
+
+CONST MD5_TRANSFORM_FUNC Md5_F[] = {
+ Tf1,
+ Tf2,
+ Tf3,
+ Tf4
+};
+
+/**
+ Perform the MD5 transform on 64 bytes data segment.
+
+ @param[in, out] Md5Ctx It includes the data segment for Md5 transform.
+**/
+VOID
+MD5Transform (
+ IN OUT MD5_CTX *Md5Ctx
+ )
+{
+ UINT32 Index1;
+ UINT32 Index2;
+ UINT32 MedStates[MD5_HASHSIZE >> 2];
+ UINT32 *Data;
+ UINT32 IndexD;
+ UINT32 IndexT;
+
+ Data = (UINT32 *) Md5Ctx->M;
+
+ //
+ // Copy MD5 states to MedStates
+ //
+ CopyMem (MedStates, Md5Ctx->States, MD5_HASHSIZE);
+
+ IndexT = 0;
+ for (Index1 = 0; Index1 < 4; Index1++) {
+ IndexD = Md5_Data[Index1][0];
+ for (Index2 = 16; Index2 > 0; Index2--) {
+ SA += (*Md5_F[Index1]) (SB, SC, SD) + Data[IndexD] + Md5_T[IndexT];
+ SA = ROTATE_LEFT (SA, Md5_S[Index1][Index2 & 3]);
+ SA += SB;
+
+ IndexD += Md5_Data[Index1][1];
+ IndexD &= 15;
+
+ IndexT++;
+ }
+ }
+
+ for (Index1 = 0; Index1 < 4; Index1++) {
+ Md5Ctx->States[Index1] += MedStates[Index1];
+ }
+}
+
+/**
+ Copy data segment into the M field of MD5_CTX structure for later transform.
+ If the length of data segment is larger than 64 bytes, then does the transform
+ immediately and the generated Md5 code is stored in the States field of MD5_CTX
+ data struct for later accumulation.
+ All of Md5 code generated for the sequential 64-bytes data segaments are be
+ accumulated in MD5Final() function.
+
+ @param[in, out] Md5Ctx The data structure of storing the original data
+ segment and the final result.
+ @param[in] Data The data wanted to be transformed.
+ @param[in] DataLen The length of data.
+**/
+VOID
+MD5UpdateBlock (
+ IN OUT MD5_CTX *Md5Ctx,
+ IN CONST UINT8 *Data,
+ IN UINTN DataLen
+ )
+{
+ UINTN Limit;
+
+ for (Limit = 64 - Md5Ctx->Count; DataLen >= 64 - Md5Ctx->Count; Limit = 64) {
+ CopyMem (Md5Ctx->M + Md5Ctx->Count, (VOID *)Data, Limit);
+ MD5Transform (Md5Ctx);
+
+ Md5Ctx->Count = 0;
+ Data += Limit;
+ DataLen -= Limit;
+ }
+
+ CopyMem (Md5Ctx->M + Md5Ctx->Count, (VOID *)Data, DataLen);
+ Md5Ctx->Count += DataLen;
+}
+
+/**
+ Initialize four 32-bits chaining variables and use them to do the Md5 transform.
+
+ @param[out] Md5Ctx The data structure of Md5.
+
+ @retval EFI_SUCCESS Initialization is ok.
+**/
+EFI_STATUS
+MD5Init (
+ OUT MD5_CTX *Md5Ctx
+ )
+{
+ ZeroMem (Md5Ctx, sizeof (*Md5Ctx));
+
+ //
+ // Set magic initialization constants.
+ //
+ Md5Ctx->States[0] = 0x67452301;
+ Md5Ctx->States[1] = 0xefcdab89;
+ Md5Ctx->States[2] = 0x98badcfe;
+ Md5Ctx->States[3] = 0x10325476;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ the external interface of Md5 algorithm
+
+ @param[in, out] Md5Ctx The data structure of storing the original data
+ segment and the final result.
+ @param[in] Data The data wanted to be transformed.
+ @param[in] DataLen The length of data.
+
+ @retval EFI_SUCCESS The transform is ok.
+ @retval Others Other errors as indicated.
+**/
+EFI_STATUS
+MD5Update (
+ IN OUT MD5_CTX *Md5Ctx,
+ IN VOID *Data,
+ IN UINTN DataLen
+ )
+{
+ if (EFI_ERROR (Md5Ctx->Status)) {
+ return Md5Ctx->Status;
+ }
+
+ MD5UpdateBlock (Md5Ctx, (CONST UINT8 *) Data, DataLen);
+ Md5Ctx->Length += DataLen;
+ return EFI_SUCCESS;
+}
+
+/**
+ Accumulate the MD5 value of every data segment and generate the finial
+ result according to MD5 algorithm.
+
+ @param[in, out] Md5Ctx The data structure of storing the original data
+ segment and the final result.
+ @param[out] HashVal The final 128-bits output.
+
+ @retval EFI_SUCCESS The transform is ok.
+ @retval Others Other errors as indicated.
+**/
+EFI_STATUS
+MD5Final (
+ IN OUT MD5_CTX *Md5Ctx,
+ OUT UINT8 *HashVal
+ )
+{
+ UINTN PadLength;
+
+ if (Md5Ctx->Status == EFI_ALREADY_STARTED) {
+ //
+ // Store Hashed value & Zeroize sensitive context information.
+ //
+ CopyMem (HashVal, (UINT8 *) Md5Ctx->States, MD5_HASHSIZE);
+ ZeroMem ((UINT8 *)Md5Ctx, sizeof (*Md5Ctx));
+
+ return EFI_SUCCESS;
+ }
+
+ if (EFI_ERROR (Md5Ctx->Status)) {
+ return Md5Ctx->Status;
+ }
+
+ PadLength = Md5Ctx->Count >= 56 ? 120 : 56;
+ PadLength -= Md5Ctx->Count;
+ MD5UpdateBlock (Md5Ctx, Md5HashPadding, PadLength);
+ Md5Ctx->Length = LShiftU64 (Md5Ctx->Length, 3);
+ MD5UpdateBlock (Md5Ctx, (CONST UINT8 *) &Md5Ctx->Length, 8);
+
+ ZeroMem (Md5Ctx->M, sizeof (Md5Ctx->M));
+ Md5Ctx->Length = 0;
+ Md5Ctx->Status = EFI_ALREADY_STARTED;
+ return MD5Final (Md5Ctx, HashVal);
+}
+
diff --git a/Platforms/APM/XGene/Applications/UpgradeFirmware/Md5.h b/Platforms/APM/XGene/Applications/UpgradeFirmware/Md5.h
new file mode 100755
index 0000000..026f3f4
--- /dev/null
+++ b/Platforms/APM/XGene/Applications/UpgradeFirmware/Md5.h
@@ -0,0 +1,79 @@
+/** @file
+ Header file for Md5.
+
+Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MD5_H_
+#define _MD5_H_
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#define MD5_HASHSIZE 16
+
+typedef struct _MD5_CTX {
+ EFI_STATUS Status;
+ UINT64 Length;
+ UINT32 States[MD5_HASHSIZE / sizeof (UINT32)];
+ UINT8 M[64];
+ UINTN Count;
+} MD5_CTX;
+
+/**
+ Initialize four 32-bits chaining variables and use them to do the Md5 transform.
+
+ @param[out] Md5Ctx The data structure of Md5.
+
+ @retval EFI_SUCCESS Initialization is ok.
+**/
+EFI_STATUS
+MD5Init (
+ OUT MD5_CTX *Md5Ctx
+ );
+
+/**
+ the external interface of Md5 algorithm
+
+ @param[in, out] Md5Ctx The data structure of storing the original data
+ segment and the final result.
+ @param[in] Data The data wanted to be transformed.
+ @param[in] DataLen The length of data.
+
+ @retval EFI_SUCCESS The transform is ok.
+ @retval Others Other errors as indicated.
+**/
+EFI_STATUS
+MD5Update (
+ IN OUT MD5_CTX *Md5Ctx,
+ IN VOID *Data,
+ IN UINTN DataLen
+ );
+
+/**
+ Accumulate the MD5 value of every data segment and generate the finial
+ result according to MD5 algorithm.
+
+ @param[in, out] Md5Ctx The data structure of storing the original data
+ segment and the final result.
+ @param[out] HashVal The final 128-bits output.
+
+ @retval EFI_SUCCESS The transform is ok.
+ @retval Others Other errors as indicated.
+**/
+EFI_STATUS
+MD5Final (
+ IN OUT MD5_CTX *Md5Ctx,
+ OUT UINT8 *HashVal
+ );
+
+#endif
diff --git a/Platforms/APM/XGene/Applications/UpgradeFirmware/Slimpro.c b/Platforms/APM/XGene/Applications/UpgradeFirmware/Slimpro.c
new file mode 100644
index 0000000..9d114d7
--- /dev/null
+++ b/Platforms/APM/XGene/Applications/UpgradeFirmware/Slimpro.c
@@ -0,0 +1,183 @@
+/**
+ * Copyright (c) 2014, AppliedMicro Corp. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ **/
+
+#include "Slimpro.h"
+#include <Library/SlimproLib.h>
+
+#define EEPROM_PAGE_SIZE (1 << PcdGet32(EepromPageWriteBits))
+#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1))
+
+EFI_STATUS
+EFIAPI
+EepromRead (
+ UINTN Offset,
+ CHAR8 *Buffer,
+ UINT32 Size
+ )
+{
+ UINTN DevAddr;
+ UINTN End = Offset + Size;
+ UINTN BlkOff;
+ UINT32 aLen, Len, MaxLen;
+ CHAR8 Addr[3];
+ EFI_STATUS Ret;
+
+ DevAddr = PcdGet32(EepromAddr);
+ Ret = EFI_SUCCESS;
+
+ while (Offset < End) {
+ BlkOff = Offset & 0xFF; /* block Offset */
+ if (PcdGet32(EepromAddrLen) == 1) {
+ Addr[0] = Offset >> 8; /* block number */
+ Addr[1] = BlkOff; /* block Offset */
+ aLen = 2;
+ } else {
+ Addr[0] = Offset >> 16; /* block number */
+ Addr[1] = Offset >> 8; /* upper Address octet */
+ Addr[2] = BlkOff; /* lower Address octet */
+ aLen = 3;
+ }
+
+ Addr[0] |= DevAddr; /* insert device Address */
+
+ Len = End - Offset;
+
+ if (PcdGet32(EepromPageWriteBits) > 0)
+ MaxLen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(BlkOff);
+ else
+ MaxLen = 0x100 - BlkOff;
+
+ if (Len > MaxLen)
+ Len = MaxLen;
+
+ if (I2c_Read (Addr[0], Offset, aLen-1, (UINT8*) Buffer, Len) != 0)
+ Ret = EFI_DEVICE_ERROR;
+
+ Buffer += Len;
+ Offset += Len;
+ }
+
+ return Ret;
+}
+
+EFI_STATUS
+EFIAPI
+EepromWrite (
+ UINTN Offset,
+ CHAR8 *Buffer,
+ UINT32 Size
+ )
+{
+ UINTN DevAddr;
+ UINTN End = Offset + Size;
+ UINTN BlkOff;
+ UINT32 Crc_s,Crc_d;
+ CHAR8 *CrcBuffer = NULL;
+ CHAR8* BufferSrc = Buffer;
+ UINTN OffsetSrc = Offset;
+ UINT32 aLen, Len, MaxLen;
+ CHAR8 Addr[3];
+ EFI_STATUS Ret;
+ EFI_TPL OriginalTPL;
+
+ DevAddr = PcdGet32(EepromAddr);
+
+ // Raise TPL to TPL_HIGH to stop anyone from interrupting us.
+ OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+
+ Ret = EFI_SUCCESS;
+
+ INFO("Slimpro updating.... ");
+
+ XGeneBMCStart(FALSE);
+
+ while (Offset < End) {
+
+ BlkOff = Offset & 0xFF; /* block Offset */
+ if (PcdGet32(EepromAddrLen) == 1) {
+ Addr[0] = Offset >> 8; /* block number */
+ Addr[1] = BlkOff; /* block Offset */
+ aLen = 2;
+ } else {
+ Addr[0] = Offset >> 16; /* block number */
+ Addr[1] = Offset >> 8; /* upper Address octet */
+ Addr[2] = BlkOff; /* lower Address octet */
+ aLen = 3;
+ }
+
+ Addr[0] |= DevAddr; /* insert device Address */
+
+ Len = End - Offset;
+
+ if (PcdGet32(EepromPageWriteBits) > 0)
+ MaxLen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(BlkOff);
+ else
+ MaxLen = 0x100 - BlkOff;
+
+ if (Len > MaxLen)
+ Len = MaxLen;
+
+ Crc_s = Crc_d = 0;
+ gBS->CalculateCrc32 ((VOID *)Buffer, Len, &Crc_s);
+ if (I2c_Write (Addr[0], Offset, aLen-1, (UINT8*) Buffer, Len) != 0) {
+ Ret = EFI_DEVICE_ERROR;
+ goto EXIT;
+ }
+ Print(L"#");
+
+ Buffer += Len;
+ Offset += Len;
+ }
+ Print(L"\n");
+
+ if (!EFI_ERROR(Ret)) {
+ INFO("Slimpro Validating.... ");
+ Crc_s = Crc_d;
+ gBS->CalculateCrc32 ((VOID *)BufferSrc, Size, &Crc_s);
+ DBG("Slimpro Source CRC32:0x%lx ", Crc_s);
+ CrcBuffer = AllocateZeroPool (Size);
+ if (!CrcBuffer) {
+ ERROR("Out of resources\n");
+ return EFI_INVALID_PARAMETER;
+ }
+ Ret = EepromRead(OffsetSrc, CrcBuffer, Size);
+ if (EFI_ERROR(Ret)){
+ DBG("Failed to read slimpro firmware\n");
+ goto EXIT;
+ }
+ gBS->CalculateCrc32((VOID *)CrcBuffer, Size, &Crc_d);
+ DBG("Destination CRC32:0x%lx\n", Crc_d);
+ if (Crc_s == Crc_d) {
+ INFO("Update slimpro firmware successful\n");
+ }
+ else {
+ ERROR("Update slimpro firmware fail\n");
+ Ret = EFI_DEVICE_ERROR;
+ }
+ }
+EXIT:
+ if (CrcBuffer)
+ FreePool(CrcBuffer);
+
+ // Interruptions can resume.
+ gBS->RestoreTPL (OriginalTPL);
+
+ return Ret;
+}
+
+EFI_STATUS
+EFIAPI
+EepromInit (VOID)
+{
+ return I2c_Probe(PcdGet32(EepromAddr));
+}
diff --git a/Platforms/APM/XGene/Applications/UpgradeFirmware/Slimpro.h b/Platforms/APM/XGene/Applications/UpgradeFirmware/Slimpro.h
new file mode 100644
index 0000000..9e0cd22
--- /dev/null
+++ b/Platforms/APM/XGene/Applications/UpgradeFirmware/Slimpro.h
@@ -0,0 +1,39 @@
+/**
+ * Copyright (c) 2014, AppliedMicro Corp. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ **/
+
+#ifndef _SLIMPRO_H_
+#define _SLIMPRO_H_
+
+#include "UpgradeFirmware.h"
+
+EFI_STATUS
+EFIAPI
+EepromInit (VOID);
+
+EFI_STATUS
+EFIAPI
+EepromRead (
+ UINTN Offset,
+ CHAR8 *Buffer,
+ UINT32 Size
+ );
+
+EFI_STATUS
+EFIAPI
+EepromWrite (
+ UINTN Offset,
+ CHAR8 *Buffer,
+ UINT32 Size
+ );
+
+#endif /* _SLIMPRO_H_ */
diff --git a/Platforms/APM/XGene/Applications/UpgradeFirmware/UpgradeFirmware.c b/Platforms/APM/XGene/Applications/UpgradeFirmware/UpgradeFirmware.c
new file mode 100755
index 0000000..406f52a
--- /dev/null
+++ b/Platforms/APM/XGene/Applications/UpgradeFirmware/UpgradeFirmware.c
@@ -0,0 +1,542 @@
+/**
+ * Copyright (c) 2014, AppliedMicro Corp. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ **/
+
+#include "UpgradeFirmware.h"
+#include "Slimpro.h"
+#include "Md5.h"
+
+#define BUFFER_MD5_STRING_LEN 32
+#define BUFFER_READ_LEN 8192
+#define MAX_PATH 512
+#define MAX_SIZE_NUMBER_STR 5
+
+#define TIANOCORE_FIRMWARE 0
+#define SLIMPRO_FIRMWARE 1
+#define MAX_FIRMWARE_LIST 2
+
+STATIC MD5_CTX gMd5Ctx;
+STATIC UINTN gNumFirmwares;
+struct FirmwareCtx{
+ UINTN Type;
+ CHAR8 Md5[BUFFER_MD5_STRING_LEN + 1];
+ CHAR16 Path[MAX_PATH]; /* Unicode path */
+};
+
+STATIC
+EFI_STATUS
+OpenFile(
+ IN CHAR16 *FilePath,
+ OUT SHELL_FILE_HANDLE *FileHandle
+ )
+{
+ EFI_STATUS Status;
+ Status = ShellOpenFileByName(FilePath, FileHandle,
+ EFI_FILE_MODE_READ, EFI_FILE_READ_ONLY);
+ if (EFI_ERROR(Status)) {
+ ERROR("Can't open file:%s. Error code:%d\n", FilePath, Status);
+ return Status;
+ }
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+GetStringFromLine(
+ IN CHAR16 *Buffer,
+ IN OUT UINTN *Size,
+ OUT CHAR8 *AsciStr,
+ IN UINTN Len
+ )
+{
+ BOOLEAN HasChar = FALSE;
+ INTN Count;
+ UINTN Num = 0;
+
+ for (Count = 0; Count < *Size && Num < Len - 1; Count++) {
+ /* This doesn't work for big endian */
+ if ((CHAR8)Buffer[Count] == ' ' || (CHAR8)Buffer[Count] == '\t'
+ || (CHAR8)Buffer[Count] == '\r' || (CHAR8)Buffer[Count] == '\n') {
+ if (!HasChar)
+ continue;
+ break;
+ } else {
+ if (!HasChar)
+ HasChar = TRUE;
+ AsciStr[Num++] = *(CHAR8*)(&Buffer[Count]);
+ }
+ }
+ if (Count < *Size)
+ *Size = Count + 1;
+ if (HasChar) {
+ AsciStr[Num] = '\0';
+ return EFI_SUCCESS;
+ }
+ return EFI_INVALID_PARAMETER;
+}
+
+STATIC
+EFI_STATUS
+ParseFirmwareCtxFromFile (
+ IN SHELL_FILE_HANDLE FileHandle,
+ OUT struct FirmwareCtx *ListCtx,
+ IN UINTN ListLen
+ )
+{
+ EFI_STATUS Status;
+ CHAR16 *BufferTemp;
+ UINTN ReadLen = 0;
+ UINTN Len;
+#ifdef APPS_DEBUG
+ INTN Count;
+#endif
+ BOOLEAN isAscii;
+ CHAR8 NumberStr[MAX_SIZE_NUMBER_STR];
+ CHAR16 *Pointer;
+ CHAR8 AsciiPath[MAX_PATH];
+
+ BufferTemp = AllocateZeroPool(BUFFER_READ_LEN * sizeof(CHAR16));
+ if (!BufferTemp) {
+ ERROR("Out of Memory\n");
+ Status = EFI_NOT_READY;
+ goto EXIT;
+ }
+ gNumFirmwares = 0;
+ ReadLen = BUFFER_READ_LEN * sizeof(CHAR16);
+ Status = ShellFileHandleReadLine(FileHandle, BufferTemp,
+ &ReadLen, FALSE, &isAscii);
+ if (!isAscii) {
+ /* don't support non Ascii file */
+ Status = EFI_INVALID_PARAMETER;
+ goto EXIT;
+ }
+ while (Status == EFI_SUCCESS && gNumFirmwares < ListLen && StrLen(BufferTemp) > 0) {
+ Pointer = BufferTemp;
+ Len = StrLen(Pointer);
+ /* Parse type */
+ Status = GetStringFromLine(Pointer, &Len, NumberStr, MAX_SIZE_NUMBER_STR);
+ if (EFI_ERROR(Status)) {
+ DBG("Can't parse type of image in the line:%s\n", BufferTemp);
+ goto EXIT;
+ }
+ ListCtx[gNumFirmwares].Type = AsciiStrDecimalToUintn(NumberStr);
+ DBG("Line:%s Parsed type:%d\n", BufferTemp, ListCtx[gNumFirmwares].Type);
+
+ /* Parse MD5 */
+ Pointer += Len;
+ Len = StrLen(Pointer);
+ Status = GetStringFromLine(Pointer, &Len, ListCtx[gNumFirmwares].Md5, BUFFER_MD5_STRING_LEN + 1);
+ if (EFI_ERROR(Status)) {
+ DBG("Can't parse md5 in the line:%s\n", BufferTemp);
+ goto EXIT;
+ }
+
+ DBG("Line:%s Parsed md5:");
+#ifdef APPS_DEBUG
+ for (Count = 0; Count < BUFFER_MD5_STRING_LEN; Count++) {
+ Print(L"%c", ListCtx[gNumFirmwares].Md5[Count]);
+ }
+ Print(L"\n");
+#endif
+
+ /* Parse File path */
+ Pointer += Len;
+ Len = StrLen(Pointer);
+ Status = GetStringFromLine(Pointer, &Len, AsciiPath, MAX_PATH);
+ if (EFI_ERROR(Status)) {
+ DBG("Can't parse path in the line:%s\n", BufferTemp);
+ goto EXIT;
+ }
+ AsciiStrToUnicodeStr(AsciiPath, ListCtx[gNumFirmwares].Path);
+ DBG("Line:%s Parsed path:%s\n", BufferTemp, ListCtx[gNumFirmwares].Path);
+
+ gNumFirmwares++;
+ ReadLen = BUFFER_READ_LEN * sizeof(CHAR16);
+ Status = ShellFileHandleReadLine(FileHandle, BufferTemp,
+ &ReadLen, FALSE, &isAscii);
+ }
+ Status = EFI_SUCCESS;
+
+EXIT:
+ if (BufferTemp)
+ FreePool(BufferTemp);
+ return Status;
+}
+/***
+ Print a usage.
+
+ Print how to run the applcation
+ .
+ @param[in] Argc Number of argument tokens pointed to by Argv.
+ @param[in] Argv Array of Argc pointers to command line tokens
+***/
+STATIC VOID PrintUsage(
+ IN UINTN Argc,
+ IN CHAR16 **Argv
+ )
+{
+ Print(L"Usage: %s <Upgrade description text file>\n", Argv[0]);
+ Print(L"<Upgrade description text file> : A text file that contains information for how to upgrade\n");
+}
+
+STATIC
+EFI_STATUS
+CalculateMD5Firmware(
+ IN OUT CHAR8 *BufferMd5,
+ IN SHELL_FILE_HANDLE FileHandle
+ )
+{
+ EFI_STATUS Status;
+ CHAR8 *BufferTemp;
+ UINTN ReadLen = 0;
+ INTN Count;
+
+ BufferTemp = AllocateZeroPool(BUFFER_READ_LEN);
+ if (!BufferTemp) {
+ ERROR("Out of Memory\n");
+ Status = EFI_NOT_READY;
+ goto EXIT;
+ }
+
+ MD5Init (&gMd5Ctx);
+ ReadLen = BUFFER_READ_LEN;
+ Status = ShellReadFile(FileHandle, &ReadLen, BufferTemp);
+ while (Status == EFI_SUCCESS && ReadLen > 0) {
+ MD5Update(&gMd5Ctx, (VOID *)BufferTemp, ReadLen);
+ if (ReadLen != BUFFER_READ_LEN) {
+ /* We are in the end of file */
+ break;
+ }
+ ReadLen = BUFFER_READ_LEN;
+ Status = ShellReadFile(FileHandle, &ReadLen, BufferTemp);
+ }
+
+ MD5Final(&gMd5Ctx, (UINT8*) BufferMd5);
+
+ /* Output of BufferMd5 is 128bit(16 bytes) so we need to convert it to 32 chars string */
+ for (Count = 0; Count < 16; Count++) {
+ AsciiSPrint(BufferTemp + Count * 2, 3, "%02x", (UINT8)BufferMd5[Count]);
+ }
+
+ CopyMem(BufferMd5, BufferTemp, BUFFER_MD5_STRING_LEN);
+ BufferMd5[BUFFER_MD5_STRING_LEN] = '\0';
+
+ Status = EFI_SUCCESS;
+
+EXIT:
+ if (BufferTemp)
+ FreePool(BufferTemp);
+
+ return Status;
+}
+
+STATIC
+BOOLEAN
+CompareMd5(
+ IN CHAR8 *BufferMd5Source,
+ IN CHAR8 *BufferMd5Dest
+ )
+{
+ if (AsciiStriCmp(BufferMd5Source, BufferMd5Dest))
+ return FALSE;
+ return TRUE;
+}
+
+STATIC
+EFI_STATUS
+WriteFirmware(
+ IN SHELL_FILE_HANDLE FileHandle
+ )
+{
+ EFI_STATUS Status;
+ EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL *EfiDevicePathFromTextProtocol;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePathInstance;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePathInstanceNext;
+ EFI_BLOCK_IO_PROTOCOL *BlockIo = NULL;
+ EFI_BLOCK_IO_PROTOCOL *BlockIoNext = NULL;
+ EFI_BLOCK_IO_PROTOCOL *PointerBlockIo;
+ EFI_HANDLE BlockIoHandle = NULL;
+ EFI_HANDLE BlockIoHandleNext = NULL;
+ UINT8 *Buffer;
+ UINTN BufferSize;
+ UINTN ReadLen;
+ EFI_LBA Lba;
+ UINT64 FileSize;
+
+ Status = gBS->LocateProtocol (&gEfiDevicePathFromTextProtocolGuid, NULL, (VOID **)&EfiDevicePathFromTextProtocol);
+ if (EFI_ERROR(Status)) {
+ DBG("Failed to locate EfiDevicePathFromTextProtocol\n");
+ return Status;
+ }
+
+ DevicePathInstance = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath ((CHAR16 *) PcdGetPtr(FirmwareBlockDevicePath));
+ if (!DevicePathInstance) {
+ DBG("Failed to load device path:%s\n", (CHAR16 *) PcdGetPtr(FirmwareBlockDevicePath));
+ return EFI_NOT_FOUND;
+ }
+
+ DevicePathInstanceNext = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath ((CHAR16 *) PcdGetPtr(FirmwareBlockDevicePathNext));
+ if (!DevicePathInstanceNext) {
+ DBG("Failed to load device path:%s\n", (CHAR16 *) PcdGetPtr(FirmwareBlockDevicePathNext));
+ return EFI_NOT_FOUND;
+ }
+
+ if (gBS->LocateDevicePath(&gEfiBlockIoProtocolGuid, &DevicePathInstance, &BlockIoHandle) == EFI_NOT_FOUND) {
+ DBG("Failed to locate block IO protocol Guid\n");
+ DBG("Device path:%s\n", (CHAR16 *) PcdGetPtr(FirmwareBlockDevicePath));
+ return EFI_NOT_FOUND;
+ }
+
+ Status = gBS->OpenProtocol(BlockIoHandle, &gEfiBlockIoProtocolGuid, (VOID**)&BlockIo, gImageHandle, NULL, EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (EFI_ERROR(Status)) {
+ DBG("Failed to open block io protocol\n");
+ return Status;
+ }
+
+ ShellGetFileSize(FileHandle, &FileSize);
+ DBG("File of firmware:%ll\n", FileSize);
+ if ((UINT64)((BlockIo->Media->LastBlock + 1) * BlockIo->Media->BlockSize) < FileSize) {
+ /* we need next block IO in case firmware span multi regions */
+ DBG("Need next block IO\n");
+ if (gBS->LocateDevicePath(&gEfiBlockIoProtocolGuid, &DevicePathInstanceNext, &BlockIoHandleNext) == EFI_NOT_FOUND) {
+ DBG("Failed to locate block IO protocol Guid\n");
+ DBG("Device path:%s\n", (CHAR16 *) PcdGetPtr(FirmwareBlockDevicePathNext));
+
+ gBS->CloseProtocol(BlockIoHandle, &gEfiBlockIoProtocolGuid, gImageHandle, NULL);
+ return EFI_NOT_FOUND;
+ }
+
+ Status = gBS->OpenProtocol(BlockIoHandleNext, &gEfiBlockIoProtocolGuid, (VOID**)&BlockIoNext, gImageHandle, NULL, EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (EFI_ERROR(Status)) {
+ DBG("Failed to open block io protocol\n");
+
+ gBS->CloseProtocol(BlockIoHandle, &gEfiBlockIoProtocolGuid, gImageHandle, NULL);
+ return Status;
+ }
+ }
+ /* One block for each write */
+ if (BlockIoNext && BlockIoNext->Media->BlockSize > BlockIo->Media->BlockSize)
+ Buffer = AllocateZeroPool(BlockIoNext->Media->BlockSize);
+ else
+ Buffer = AllocateZeroPool(BlockIo->Media->BlockSize);
+
+ /* reset file position to zero */
+ ShellSetFilePosition(FileHandle, 0);
+
+ Lba = 0;
+ PointerBlockIo = BlockIo;
+ BufferSize = BlockIo->Media->BlockSize;
+ ReadLen = BufferSize;
+ Status = ShellReadFile(FileHandle, &ReadLen, Buffer);
+
+ INFO("Writing the firmware. Please wait\n");
+ while (Status == EFI_SUCCESS && ReadLen > 0) {
+ Status = PointerBlockIo->WriteBlocks(PointerBlockIo, PointerBlockIo->Media->MediaId, Lba, ReadLen, Buffer);
+ if (EFI_ERROR(Status)) {
+ DBG("Failed to write block: %d\n", Lba);
+ goto EXIT;
+ }
+ Print(L"#");
+ Lba++;
+ if (ReadLen != BufferSize) {
+ /* We are in the end of file */
+ break;
+ }
+ if (Lba > PointerBlockIo->Media->LastBlock) {
+ DBG("Switch to next block io\n");
+ BufferSize = BlockIoNext->Media->BlockSize;
+ PointerBlockIo = BlockIoNext;
+ Lba = 0;
+ }
+ ReadLen = BufferSize;
+ Status = ShellReadFile(FileHandle, &ReadLen, Buffer);
+ }
+ INFO("Upgraded firmware SUCCESSFULLY\n");
+
+EXIT:
+ if (Buffer != NULL) {
+ FreePool(Buffer);
+ }
+ gBS->CloseProtocol(BlockIoHandle, &gEfiBlockIoProtocolGuid, gImageHandle, NULL);
+ if (BlockIoHandleNext)
+ gBS->CloseProtocol(BlockIoHandleNext, &gEfiBlockIoProtocolGuid, gImageHandle, NULL);
+
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+WriteSlimproFirmware(
+ IN SHELL_FILE_HANDLE FileHandle
+ )
+{
+ EFI_STATUS Status;
+ UINT8 *Buffer = NULL;
+ VOID *Pointer;
+ UINT64 BufferSize;
+ UINT64 ReadLen;
+
+ Status = ShellGetFileSize(FileHandle, &BufferSize);
+ if (EFI_ERROR(Status)) {
+ ERROR("Failed to read slimpro firmware\n");
+ goto EXIT;
+ }
+ Buffer = AllocateZeroPool(BufferSize);
+ if (!Buffer) {
+ ERROR("Out of memory\n");
+ goto EXIT;
+ }
+ /* reset file position to zero */
+ ShellSetFilePosition(FileHandle, 0);
+
+ ReadLen = BUFFER_READ_LEN;
+ Pointer = Buffer;
+ Status = ShellReadFile(FileHandle, &ReadLen, Pointer);
+ while (Status == EFI_SUCCESS && ReadLen > 0) {
+ Pointer += ReadLen;
+ if (ReadLen < BUFFER_READ_LEN)
+ break;
+ ReadLen = BUFFER_READ_LEN;
+ Status = ShellReadFile(FileHandle, &ReadLen, Pointer);
+ }
+ if (((UINT64)Pointer - (UINT64)Buffer) != BufferSize) {
+ DBG("Can't read the whole of slimpro firmware\n");
+ goto EXIT;
+ }
+ Status = EepromWrite (0, (CHAR8 *)Buffer, (UINT32) BufferSize);
+ if (EFI_ERROR(Status)) {
+ DBG("Write slimpro FAILED\n");
+ goto EXIT;
+ }
+
+ INFO("Upgraded slimpro firmware SUCCESSFULLY\n");
+
+EXIT:
+ if (Buffer != NULL) {
+ FreePool(Buffer);
+ }
+ return Status;
+}
+
+/***
+ Print a welcoming message.
+
+ Establishes the main structure of the application.
+ @param[in] Argc Number of argument tokens pointed to by Argv.
+ @param[in] Argv Array of Argc pointers to command line tokens
+
+ @retval 0 The application exited normally.
+ @retval Other An error occurred.
+***/
+INTN
+EFIAPI
+ShellAppMain (
+ IN UINTN Argc,
+ IN CHAR16 **Argv
+ )
+{
+ EFI_STATUS Status;
+ CHAR8 BufferMd5Calculated[BUFFER_MD5_STRING_LEN + 1];
+ SHELL_FILE_HANDLE FileHandle = 0;
+ struct FirmwareCtx *ListCtx = NULL;
+ INTN Count;
+#ifdef APPS_DEBUG
+ INTN Count1;
+#endif
+
+ Status = EFI_SUCCESS;
+
+ /* First argument must be FW tianocore_mustang.fd
+ * Second argument must be text file contain checksum of the firmware
+ */
+ if (Argc != 2) {
+ Status = OpenFile(L"apm_upgrade.cmd", &FileHandle);
+ if (EFI_ERROR(Status)) {
+ PrintUsage(Argc, Argv);
+ goto EXIT;
+ }
+ } else {
+ Status = OpenFile(Argv[1], &FileHandle);
+ if (EFI_ERROR(Status)) {
+ ERROR("Failed to open file:%s\n", Argv[1]);
+ goto EXIT;
+ }
+ }
+
+ ListCtx = AllocateZeroPool (sizeof(struct FirmwareCtx) * MAX_FIRMWARE_LIST);
+ if (!ListCtx) {
+ ERROR("Out of memory\n");
+ Status = EFI_OUT_OF_RESOURCES;
+ goto EXIT;
+ }
+
+ Status = ParseFirmwareCtxFromFile(FileHandle, ListCtx, MAX_FIRMWARE_LIST);
+ if (EFI_ERROR(Status)) {
+ ERROR("Can't get content from file:%s\n", Argv[1]);
+ goto EXIT;
+ }
+
+ for (Count = 0; Count < gNumFirmwares; Count++) {
+ /* close previous opened file */
+ ShellCloseFile (&FileHandle);
+ FileHandle = 0;
+
+ Status = OpenFile(ListCtx[Count].Path, &FileHandle);
+ if (EFI_ERROR(Status)) {
+ ERROR("Failed to open file:%s\n", ListCtx[Count].Path);
+ goto EXIT;
+ }
+ Status = CalculateMD5Firmware(BufferMd5Calculated, FileHandle);
+ if (EFI_ERROR(Status)) {
+ ERROR("Failed to calculate MD5 for file:%s\n",
+ ListCtx[Count].Path);
+ goto EXIT;
+ }
+#ifdef APPS_DEBUG
+ DBG("MD5 calculated:");
+ for (Count1 = 0; Count1 < BUFFER_MD5_STRING_LEN; Count1++) {
+ AsciiPrint("%c", BufferMd5Calculated[Count1]);
+ }
+ Print(L"\n");
+#endif
+ if (CompareMd5(BufferMd5Calculated, ListCtx[Count].Md5)) {
+ DBG("Md5checksum matched for file:%s\n", ListCtx[Count].Path);
+ } else {
+ ERROR("Checksum is not matched for file:%s\n", ListCtx[Count].Path);
+ goto EXIT;
+ }
+
+ if (ListCtx[Count].Type == TIANOCORE_FIRMWARE) {
+ INFO("Writing tianocore firmware from file:%s\n", ListCtx[Count].Path);
+ Status = WriteFirmware(FileHandle);
+ if (EFI_ERROR(Status)) {
+ ERROR("Failed to write firmware from file:%s\n", ListCtx[Count].Path);
+ goto EXIT;
+ }
+ }
+ if (ListCtx[Count].Type == SLIMPRO_FIRMWARE) {
+ INFO("Writing slimpro firmware from file:%s\n", ListCtx[Count].Path);
+ Status = WriteSlimproFirmware(FileHandle);
+ if (EFI_ERROR(Status)) {
+ ERROR("Failed to write slimpro firmware from file:%s\n", ListCtx[Count].Path);
+ goto EXIT;
+ }
+ }
+ }
+
+EXIT:
+ if (FileHandle) {
+ ShellCloseFile (&FileHandle);
+ }
+
+ return (INTN)Status;
+}
diff --git a/Platforms/APM/XGene/Applications/UpgradeFirmware/UpgradeFirmware.h b/Platforms/APM/XGene/Applications/UpgradeFirmware/UpgradeFirmware.h
new file mode 100644
index 0000000..15bde45
--- /dev/null
+++ b/Platforms/APM/XGene/Applications/UpgradeFirmware/UpgradeFirmware.h
@@ -0,0 +1,66 @@
+/**
+ * Copyright (c) 2014, AppliedMicro Corp. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ **/
+
+#ifndef _UPGRADEFIRMWARE_H_
+#define _UPGRADEFIRMWARE_H_
+
+#include <Uefi.h>
+#include <Base.h>
+
+#include <Guid/FileInfo.h>
+#include <Guid/GlobalVariable.h>
+
+
+#include <Library/UefiLib.h>
+#include <Library/UefiApplicationEntryPoint.h>
+#include <Library/PathLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/FileHandleLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/ShellLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/DevicePathFromText.h>
+#include <Protocol/DevicePathToText.h>
+
+#include <Protocol/SimpleFileSystem.h>
+#include <Protocol/UnicodeCollation.h>
+#include <Protocol/BlockIo.h>
+
+#include <Library/I2C.h>
+
+//#define APPS_DEBUG 1
+#define APPS_INFO 1
+
+#ifdef APPS_DEBUG
+#define DBG(arg...) Print (L"DEBUG: " arg)
+#else
+#define DBG(arg...)
+#endif
+
+#ifdef APPS_INFO
+#define INFO(arg...) Print (L"INFO: " arg)
+#else
+#define INFO(arg...)
+#endif
+
+#define ERROR(arg...) Print (L"ERROR: " arg)
+
+#endif
diff --git a/Platforms/APM/XGene/Applications/UpgradeFirmware/UpgradeFirmware.inf b/Platforms/APM/XGene/Applications/UpgradeFirmware/UpgradeFirmware.inf
new file mode 100755
index 0000000..cf14b77
--- /dev/null
+++ b/Platforms/APM/XGene/Applications/UpgradeFirmware/UpgradeFirmware.inf
@@ -0,0 +1,54 @@
+##
+# Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+##
+
+[Defines]
+ INF_VERSION = 0x00010006
+ BASE_NAME = UpgradeFirmware
+ FILE_GUID = a912f198-7f0e-4803-b908-b757b806ec83
+ MODULE_TYPE = UEFI_APPLICATION
+ VERSION_STRING = 0.1
+ ENTRY_POINT = ShellCEntryLib
+
+[Sources]
+ UpgradeFirmware.c
+ Slimpro.c
+ Md5.c
+
+[Packages]
+ ArmPlatformPkg/APMXGenePkg/Applications/AppPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ShellPkg/ShellPkg.dec
+
+[LibraryClasses]
+ UefiLib
+ ShellCEntryLib
+ UefiBootServicesTableLib
+ PrintLib
+ PcdLib
+ BaseLib
+ MemoryAllocationLib
+ DevicePathLib
+ ShellLib
+ I2CLib
+ SlimproLib
+
+[Pcd]
+ gAppPkgTokenSpaceGuid.EepromAddrLen
+ gAppPkgTokenSpaceGuid.EepromPageWriteBits
+ gAppPkgTokenSpaceGuid.EepromAddr
+ gAppPkgTokenSpaceGuid.FirmwareBlockDevicePath
+ gAppPkgTokenSpaceGuid.FirmwareBlockDevicePathNext
+
+[Protocols]
+ gEfiBlockIoProtocolGuid
+ gEfiDevicePathFromTextProtocolGuid \ No newline at end of file
diff --git a/Platforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/AhciMode.c b/Platforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/AhciMode.c
new file mode 100755
index 0000000..1640fdf
--- /dev/null
+++ b/Platforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/AhciMode.c
@@ -0,0 +1,2260 @@
+/** @file
+ The file for AHCI mode of ATA host controller.
+
+ Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "AtaAtapiPassThru.h"
+
+/**
+ Read AHCI Operation register.
+
+ @param Base Base address.
+ @param Offset The operation register offset.
+
+ @return The register content read.
+
+**/
+UINT32
+EFIAPI
+AhciReadReg (
+ IN VOID *Base,
+ IN UINT32 Offset
+ )
+{
+ ASSERT (Base != NULL);
+ return *(volatile UINT32 *)(Base + Offset);
+}
+
+/**
+ Write AHCI Operation register.
+
+ @param Base Base address.
+ @param Offset The operation register offset.
+ @param Data The data used to write down.
+
+**/
+VOID
+EFIAPI
+AhciWriteReg (
+ IN VOID *Base,
+ IN UINT32 Offset,
+ IN UINT32 Data
+ )
+{
+ ASSERT (Base != NULL);
+ *(volatile UINT32 *)(Base + Offset) = Data;
+}
+
+VOID
+EFIAPI
+AhciWriteRegWithFlush (
+ IN VOID *Base,
+ IN UINT32 Offset,
+ IN UINT32 Data
+ )
+{
+ AhciWriteReg(Base, Offset, Data);
+ Data = AhciReadReg(Base, Offset);
+}
+
+/**
+ Do AND operation with the value of AHCI Operation register.
+
+ @param Base Base address.
+ @param Offset The operation register offset.
+ @param AndData The data used to do AND operation.
+
+**/
+VOID
+EFIAPI
+AhciAndReg (
+ IN VOID *Base,
+ IN UINT32 Offset,
+ IN UINT32 AndData
+ )
+{
+ UINT32 Data;
+
+ Data = AhciReadReg (Base, Offset);
+
+ Data &= AndData;
+
+ AhciWriteReg (Base, Offset, Data);
+}
+
+VOID
+EFIAPI
+AhciAndRegWithFlush (
+ IN VOID *Base,
+ IN UINT32 Offset,
+ IN UINT32 AndData
+ )
+{
+ UINT32 Data;
+
+ Data = AhciReadReg (Base, Offset);
+
+ Data &= AndData;
+
+ AhciWriteRegWithFlush (Base, Offset, Data);
+}
+
+/**
+ Do OR operation with the value of AHCI Operation register.
+
+ @param Base Base address.
+ @param Offset The operation register offset.
+ @param OrData The data used to do OR operation.
+
+**/
+VOID
+EFIAPI
+AhciOrReg (
+ IN VOID *Base,
+ IN UINT32 Offset,
+ IN UINT32 OrData
+ )
+{
+ UINT32 Data;
+
+ Data = AhciReadReg (Base, Offset);
+
+ Data |= OrData;
+
+ AhciWriteReg (Base, Offset, Data);
+}
+
+VOID
+EFIAPI
+AhciOrRegWithFlush (
+ IN VOID *Base,
+ IN UINT32 Offset,
+ IN UINT32 OrData
+ )
+{
+ UINT32 Data;
+
+ Data = AhciReadReg (Base, Offset);
+
+ Data |= OrData;
+
+ AhciWriteRegWithFlush (Base, Offset, Data);
+}
+
+/**
+ Wait for the value of the specified MMIO register set to the test value.
+
+ @param Base Base address.
+ @param Offset The MMIO address to test.
+ @param MaskValue The mask value of memory.
+ @param TestValue The test value of memory.
+ @param Timeout The time out value for wait memory set, uses 100ns as a unit.
+
+ @retval EFI_TIMEOUT The MMIO setting is time out.
+ @retval EFI_SUCCESS The MMIO is correct set.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciWaitMmioSet (
+ IN VOID *Base,
+ IN UINTN Offset,
+ IN UINT32 MaskValue,
+ IN UINT32 TestValue,
+ IN UINT64 Timeout
+ )
+{
+ UINT32 Value;
+ UINT32 Delay;
+
+ Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);
+
+ do {
+ //
+ // Access PCI MMIO space to see if the value is the tested one.
+ //
+ Value = AhciReadReg (Base, (UINT32) Offset) & MaskValue;
+
+ if (Value == TestValue) {
+ return EFI_SUCCESS;
+ }
+
+ //
+ // Stall for 100 microseconds.
+ //
+ MicroSecondDelay (100);
+
+ Delay--;
+
+ } while (Delay > 0);
+
+ return EFI_TIMEOUT;
+}
+
+/**
+ Wait for the value of the specified system memory set to the test value.
+
+ @param Address The system memory address to test.
+ @param MaskValue The mask value of memory.
+ @param TestValue The test value of memory.
+ @param Timeout The time out value for wait memory set, uses 100ns as a unit.
+
+ @retval EFI_TIMEOUT The system memory setting is time out.
+ @retval EFI_SUCCESS The system memory is correct set.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciWaitMemSet (
+ IN EFI_PHYSICAL_ADDRESS Address,
+ IN UINT32 MaskValue,
+ IN UINT32 TestValue,
+ IN UINT64 Timeout
+ )
+{
+ UINT32 Value;
+ UINT32 Delay;
+
+ Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);
+
+ do {
+ //
+ // Access sytem memory to see if the value is the tested one.
+ //
+ // The system memory pointed by Address will be updated by the
+ // SATA Host Controller, "volatile" is introduced to prevent
+ // compiler from optimizing the access to the memory address
+ // to only read once.
+ //
+ Value = *(volatile UINT32 *) Address;
+ Value &= MaskValue;
+
+ if (Value == TestValue) {
+ return EFI_SUCCESS;
+ }
+
+ //
+ // Stall for 100 microseconds.
+ //
+ MicroSecondDelay (100);
+
+ Delay--;
+
+ } while (Delay > 0);
+
+ return EFI_TIMEOUT;
+}
+
+/**
+ Check the memory status to the test value.
+
+ @param[in] Address The memory address to test.
+ @param[in] MaskValue The mask value of memory.
+ @param[in] TestValue The test value of memory.
+ @param[in, out] RetryTimes The retry times value for waitting memory set. If 0, then just try once.
+
+ @retval EFI_NOTREADY The memory is not set.
+ @retval EFI_TIMEOUT The memory setting retry times out.
+ @retval EFI_SUCCESS The memory is correct set.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciCheckMemSet (
+ IN EFI_PHYSICAL_ADDRESS Address,
+ IN UINT32 MaskValue,
+ IN UINT32 TestValue,
+ IN OUT UINTN *RetryTimes OPTIONAL
+ )
+{
+ UINT32 Value;
+
+ if (RetryTimes != NULL) {
+ (*RetryTimes)--;
+ }
+
+ Value = *(volatile UINT32 *) Address;
+ Value &= MaskValue;
+
+ if (Value == TestValue) {
+ return EFI_SUCCESS;
+ }
+
+ if ((RetryTimes != NULL) && (*RetryTimes == 0)) {
+ return EFI_TIMEOUT;
+ } else {
+ return EFI_NOT_READY;
+ }
+}
+
+/**
+ Check if the device is still on port. It also checks if the AHCI controller
+ supports the address and data count will be transferred.
+
+ @param Base Base address.
+ @param Port The number of port.
+
+ @retval EFI_SUCCESS The device is attached to port and the transfer data is
+ supported by AHCI controller.
+ @retval EFI_UNSUPPORTED The transfer address and count is not supported by AHCI
+ controller.
+ @retval EFI_NOT_READY The physical communication between AHCI controller and device
+ is not ready.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciCheckDeviceStatus (
+ IN VOID *Base,
+ IN UINT8 Port
+ )
+{
+ UINT32 Data;
+ UINT32 Offset;
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
+
+ Data = AhciReadReg (Base, Offset) & EFI_AHCI_PORT_SSTS_DET_MASK;
+
+ if (Data == EFI_AHCI_PORT_SSTS_DET_PCE) {
+ return EFI_SUCCESS;
+ }
+
+ return EFI_NOT_READY;
+}
+
+/**
+
+ Clear the port interrupt and error status. It will also clear
+ HBA interrupt status.
+
+ @param Base Base address.
+ @param Port The number of port.
+
+**/
+VOID
+EFIAPI
+AhciClearPortStatus (
+ IN VOID *Base,
+ IN UINT8 Port
+ )
+{
+ UINT32 Offset;
+
+ //
+ // Clear any error status
+ //
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
+ AhciWriteRegWithFlush (Base, Offset, AhciReadReg (Base, Offset));
+
+ //
+ // Clear any port interrupt status
+ //
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
+ AhciWriteRegWithFlush (Base, Offset, AhciReadReg (Base, Offset));
+
+ //
+ // Clear any HBA interrupt status
+ //
+ AhciWriteRegWithFlush (Base, EFI_AHCI_IS_OFFSET, AhciReadReg (Base, EFI_AHCI_IS_OFFSET));
+}
+
+/**
+ This function is used to dump the Status Registers and if there is ERR bit set
+ in the Status Register, the Error Register's value is also be dumped.
+
+ @param Base Base address.
+ @param Port The number of port.
+ @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
+
+**/
+VOID
+EFIAPI
+AhciDumpPortStatus (
+ IN VOID *Base,
+ IN UINT8 Port,
+ IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
+ )
+{
+ UINT32 Offset;
+ UINT32 Data;
+
+ ASSERT (Base != NULL);
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
+ Data = AhciReadReg (Base, Offset);
+
+ if (AtaStatusBlock != NULL) {
+ ZeroMem (AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
+
+ AtaStatusBlock->AtaStatus = (UINT8)Data;
+ if ((AtaStatusBlock->AtaStatus & BIT0) != 0) {
+ AtaStatusBlock->AtaError = (UINT8)(Data >> 8);
+ }
+ }
+}
+
+
+/**
+ Enable the FIS running for giving port.
+
+ @param Base Base address.
+ @param Port The number of port.
+ @param Timeout The timeout value of enabling FIS, uses 100ns as a unit.
+
+ @retval EFI_DEVICE_ERROR The FIS enable setting fails.
+ @retval EFI_TIMEOUT The FIS enable setting is time out.
+ @retval EFI_SUCCESS The FIS enable successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciEnableFisReceive (
+ IN VOID *Base,
+ IN UINT8 Port,
+ IN UINT64 Timeout
+ )
+{
+ UINT32 Offset;
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
+ AhciOrRegWithFlush (Base, Offset, EFI_AHCI_PORT_CMD_FRE);
+
+// return AhciWaitMmioSet (
+// Base,
+// Offset,
+// EFI_AHCI_PORT_CMD_FR,
+// EFI_AHCI_PORT_CMD_FR,
+// Timeout
+// );
+ return EFI_SUCCESS;
+}
+
+/**
+ Disable the FIS running for giving port.
+
+ @param Base Base address.
+ @param Port The number of port.
+ @param Timeout The timeout value of disabling FIS, uses 100ns as a unit.
+
+ @retval EFI_DEVICE_ERROR The FIS disable setting fails.
+ @retval EFI_TIMEOUT The FIS disable setting is time out.
+ @retval EFI_UNSUPPORTED The port is in running state.
+ @retval EFI_SUCCESS The FIS disable successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciDisableFisReceive (
+ IN VOID *Base,
+ IN UINT8 Port,
+ IN UINT64 Timeout
+ )
+{
+ UINT32 Offset;
+ UINT32 Data;
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
+ Data = AhciReadReg (Base, Offset);
+
+ //
+ // Before disabling Fis receive, the DMA engine of the port should NOT be in running status.
+ //
+ if ((Data & (EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_CR)) != 0) {
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // Check if the Fis receive DMA engine for the port is running.
+ //
+ if ((Data & EFI_AHCI_PORT_CMD_FR) != EFI_AHCI_PORT_CMD_FR) {
+ return EFI_SUCCESS;
+ }
+
+ AhciAndRegWithFlush (Base, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_FRE));
+
+ return EFI_SUCCESS;
+// return AhciWaitMmioSet (
+// Base,
+// Offset,
+// EFI_AHCI_PORT_CMD_FR,
+// 0,
+// Timeout
+// );
+}
+
+
+
+/**
+ Build the command list, command table and prepare the fis receiver.
+
+ @param Base Base address.
+ @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
+ @param Port The number of port.
+ @param PortMultiplier The timeout value of stop.
+ @param CommandFis The control fis will be used for the transfer.
+ @param CommandList The command list will be used for the transfer.
+ @param AtapiCommand The atapi command will be used for the transfer.
+ @param AtapiCommandLength The length of the atapi command.
+ @param CommandSlotNumber The command slot will be used for the transfer.
+ @param DataPhysicalAddr The pointer to the data buffer pci bus master address.
+ @param DataLength The data count to be transferred.
+
+**/
+VOID
+EFIAPI
+AhciBuildCommand (
+ IN VOID *Base,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN EFI_AHCI_COMMAND_FIS *CommandFis,
+ IN EFI_AHCI_COMMAND_LIST *CommandList,
+ IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
+ IN UINT8 AtapiCommandLength,
+ IN UINT8 CommandSlotNumber,
+ IN OUT VOID *DataPhysicalAddr,
+ IN UINT32 DataLength
+ )
+{
+ UINT64 BaseAddr;
+ UINT32 PrdtNumber;
+ UINT32 PrdtIndex;
+ UINTN RemainedData;
+ UINT64 MemAddr;
+ DATA_64 Data64;
+ UINT32 Offset;
+
+ //
+ // Filling the PRDT
+ //
+ PrdtNumber = (DataLength + EFI_AHCI_MAX_DATA_PER_PRDT - 1) / EFI_AHCI_MAX_DATA_PER_PRDT;
+
+ //
+ // According to AHCI 1.3 spec, a PRDT entry can point to a maximum 4MB data block.
+ // It also limits that the maximum amount of the PRDT entry in the command table
+ // is 65535.
+ //
+ ASSERT (PrdtNumber <= 65535);
+
+ Data64.Uint64 = (UINT64) (AhciRegisters->AhciRFis) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;
+
+ BaseAddr = Data64.Uint64;
+ ZeroMem ((VOID *)((UINT64) BaseAddr), sizeof (EFI_AHCI_RECEIVED_FIS));
+
+ ZeroMem (AhciRegisters->AhciCommandTable, sizeof (EFI_AHCI_COMMAND_TABLE));
+ CommandFis->AhciCFisPmNum = PortMultiplier;
+
+ CopyMem (&AhciRegisters->AhciCommandTable->CommandFis, CommandFis, sizeof (EFI_AHCI_COMMAND_FIS));
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
+ if (AtapiCommand != NULL) {
+ CopyMem (
+ &AhciRegisters->AhciCommandTable->AtapiCmd,
+ AtapiCommand,
+ AtapiCommandLength
+ );
+
+ CommandList->AhciCmdA = 1;
+ CommandList->AhciCmdP = 1;
+ CommandList->AhciCmdC = (DataLength == 0) ? 1 : 0;
+
+ AhciOrReg (Base, Offset, (EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
+ } else {
+ AhciAndReg (Base, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
+ }
+
+ RemainedData = DataLength;
+ MemAddr = (UINT64) DataPhysicalAddr;
+ CommandList->AhciCmdPrdtl = PrdtNumber;
+ for (PrdtIndex = 0; PrdtIndex < PrdtNumber; PrdtIndex++) {
+ if (RemainedData < EFI_AHCI_MAX_DATA_PER_PRDT) {
+ AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = (UINT32)RemainedData - 1;
+ } else {
+ AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = EFI_AHCI_MAX_DATA_PER_PRDT - 1;
+ }
+
+ Data64.Uint64 = (UINT64)MemAddr;
+ AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDba = Data64.Uint32.Lower32;
+ AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbau = Data64.Uint32.Upper32;
+ RemainedData -= EFI_AHCI_MAX_DATA_PER_PRDT;
+ MemAddr += EFI_AHCI_MAX_DATA_PER_PRDT;
+ }
+
+ //
+ // Set the last PRDT to Interrupt On Complete
+ //
+ if (PrdtNumber > 0) {
+ AhciRegisters->AhciCommandTable->PrdtTable[PrdtNumber - 1].AhciPrdtIoc = 1;
+ }
+ CopyMem (
+ (VOID *) ((UINT64) AhciRegisters->AhciCmdList + (UINT64) CommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST)),
+ CommandList,
+ sizeof (EFI_AHCI_COMMAND_LIST)
+ );
+
+ Data64.Uint64 = (UINT64) AhciRegisters->AhciCommandTable;
+ AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtba = Data64.Uint32.Lower32;
+ AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtbau = Data64.Uint32.Upper32;
+ AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdPmp = PortMultiplier;
+}
+
+/**
+ Buid a command FIS.
+
+ @param CmdFis A pointer to the EFI_AHCI_COMMAND_FIS data structure.
+ @param AtaCommandBlock A pointer to the AhciBuildCommandFis data structure.
+
+**/
+VOID
+EFIAPI
+AhciBuildCommandFis (
+ IN OUT EFI_AHCI_COMMAND_FIS *CmdFis,
+ IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock
+ )
+{
+ ZeroMem (CmdFis, sizeof (EFI_AHCI_COMMAND_FIS));
+
+ CmdFis->AhciCFisType = EFI_AHCI_FIS_REGISTER_H2D;
+ //
+ // Indicator it's a command
+ //
+ CmdFis->AhciCFisCmdInd = 0x1;
+ CmdFis->AhciCFisCmd = AtaCommandBlock->AtaCommand;
+
+ CmdFis->AhciCFisFeature = AtaCommandBlock->AtaFeatures;
+ CmdFis->AhciCFisFeatureExp = AtaCommandBlock->AtaFeaturesExp;
+
+ CmdFis->AhciCFisSecNum = AtaCommandBlock->AtaSectorNumber;
+ CmdFis->AhciCFisSecNumExp = AtaCommandBlock->AtaSectorNumberExp;
+
+ CmdFis->AhciCFisClyLow = AtaCommandBlock->AtaCylinderLow;
+ CmdFis->AhciCFisClyLowExp = AtaCommandBlock->AtaCylinderLowExp;
+
+ CmdFis->AhciCFisClyHigh = AtaCommandBlock->AtaCylinderHigh;
+ CmdFis->AhciCFisClyHighExp = AtaCommandBlock->AtaCylinderHighExp;
+
+ CmdFis->AhciCFisSecCount = AtaCommandBlock->AtaSectorCount;
+ CmdFis->AhciCFisSecCountExp = AtaCommandBlock->AtaSectorCountExp;
+
+ CmdFis->AhciCFisDevHead = (UINT8) (AtaCommandBlock->AtaDeviceHead | 0xE0);
+}
+
+/**
+ Start a PIO data transfer on specific port.
+
+ @param[in] Base Base address.
+ @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
+ @param[in] Port The number of port.
+ @param[in] PortMultiplier The timeout value of stop.
+ @param[in] AtapiCommand The atapi command will be used for the
+ transfer.
+ @param[in] AtapiCommandLength The length of the atapi command.
+ @param[in] Read The transfer direction.
+ @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.
+ @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
+ @param[in, out] MemoryAddr The pointer to the data buffer.
+ @param[in] DataCount The data count to be transferred.
+ @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
+ @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
+ used by non-blocking mode.
+
+ @retval EFI_DEVICE_ERROR The PIO data transfer abort with error occurs.
+ @retval EFI_TIMEOUT The operation is time out.
+ @retval EFI_UNSUPPORTED The device is not ready for transfer.
+ @retval EFI_SUCCESS The PIO data transfer executes successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciPioTransfer (
+ IN VOID *Base,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
+ IN UINT8 AtapiCommandLength,
+ IN BOOLEAN Read,
+ IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
+ IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
+ IN OUT VOID *MemoryAddr,
+ IN UINT32 DataCount,
+ IN UINT64 Timeout,
+ IN ATA_NONBLOCK_TASK *Task
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS FisBaseAddr;
+ UINTN Offset;
+ UINT32 Delay;
+ EFI_AHCI_COMMAND_FIS CFis;
+ EFI_AHCI_COMMAND_LIST CmdList;
+ UINT32 PortTfd;
+ UINT32 PrdCount;
+
+ Timeout *= 10;
+ //
+ // Package read needed
+ //
+ AhciBuildCommandFis (&CFis, AtaCommandBlock);
+
+ ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
+
+ CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
+ CmdList.AhciCmdW = Read ? 0 : 1;
+
+ AhciBuildCommand (
+ Base,
+ AhciRegisters,
+ Port,
+ PortMultiplier,
+ &CFis,
+ &CmdList,
+ AtapiCommand,
+ AtapiCommandLength,
+ 0,
+ (VOID *)MemoryAddr,
+ DataCount
+ );
+
+ Status = AhciStartCommand (
+ Base,
+ Port,
+ 0,
+ Timeout
+ );
+ if (EFI_ERROR (Status)) {
+ goto Exit;
+ }
+
+ //
+ // Check the status and wait the driver sending data
+ //
+ FisBaseAddr = (UINT64)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
+
+ if (Read && (AtapiCommand == 0)) {
+ //
+ // Wait device sends the PIO setup fis before data transfer
+ //
+ Status = EFI_TIMEOUT;
+ Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);
+ do {
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
+ PortTfd = AhciReadReg (Base, (UINT32) Offset);
+
+ if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
+ Status = EFI_DEVICE_ERROR;
+ break;
+ }
+ Offset = FisBaseAddr + EFI_AHCI_PIO_FIS_OFFSET;
+
+
+ Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_PIO_SETUP, 0);
+ if (!EFI_ERROR (Status)) {
+ PrdCount = *(volatile UINT32 *) (&(AhciRegisters->AhciCmdList[0].AhciCmdPrdbc));
+ if (PrdCount == DataCount) {
+ break;
+ }
+ }
+
+ Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
+ Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_REGISTER_D2H, 0);
+ if (!EFI_ERROR (Status)) {
+ Status = EFI_DEVICE_ERROR;
+ break;
+ }
+
+ //
+ // Stall for 100 microseconds.
+ //
+ MicroSecondDelay(100);
+
+ Delay--;
+ } while (Delay > 0);
+ } else {
+ //
+ // Wait for D2H Fis is received
+ //
+ Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
+ Status = AhciWaitMemSet (
+ Offset,
+ EFI_AHCI_FIS_TYPE_MASK,
+ EFI_AHCI_FIS_REGISTER_D2H,
+ Timeout
+ );
+
+ if (EFI_ERROR (Status)) {
+ goto Exit;
+ }
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
+ PortTfd = AhciReadReg (Base, (UINT32) Offset);
+ if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
+ Status = EFI_DEVICE_ERROR;
+ }
+ }
+
+
+Exit:
+ AhciStopCommand (
+ Base,
+ Port,
+ Timeout
+ );
+
+ AhciDisableFisReceive (
+ Base,
+ Port,
+ Timeout
+ );
+
+ AhciDumpPortStatus (Base, Port, AtaStatusBlock);
+ return Status;
+}
+
+/**
+ Start a DMA data transfer on specific port
+
+ @param[in] Instance The ATA_ATAPI_PASS_THRU_INSTANCE protocol instance.
+ @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
+ @param[in] Port The number of port.
+ @param[in] PortMultiplier The timeout value of stop.
+ @param[in] AtapiCommand The atapi command will be used for the
+ transfer.
+ @param[in] AtapiCommandLength The length of the atapi command.
+ @param[in] Read The transfer direction.
+ @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.
+ @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
+ @param[in, out] MemoryAddr The pointer to the data buffer.
+ @param[in] DataCount The data count to be transferred.
+ @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
+ @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
+ used by non-blocking mode.
+
+ @retval EFI_DEVICE_ERROR The DMA data transfer abort with error occurs.
+ @retval EFI_TIMEOUT The operation is time out.
+ @retval EFI_UNSUPPORTED The device is not ready for transfer.
+ @retval EFI_SUCCESS The DMA data transfer executes successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciDmaTransfer (
+ IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
+ IN UINT8 AtapiCommandLength,
+ IN BOOLEAN Read,
+ IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
+ IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
+ IN OUT VOID *MemoryAddr,
+ IN UINT32 DataCount,
+ IN UINT64 Timeout,
+ IN ATA_NONBLOCK_TASK *Task
+ )
+{
+ EFI_STATUS Status;
+ UINTN Offset;
+ EFI_AHCI_COMMAND_FIS CFis;
+ EFI_AHCI_COMMAND_LIST CmdList;
+ UINT64 FisBaseAddr;
+ UINT32 PortTfd;
+ VOID *Base;
+
+ EFI_TPL OldTpl;
+
+ if (Instance->Mode != EfiAtaAhciMode) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Base = Instance->AhciRegisters.MapBaseAddress;
+
+ if (!Base) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Before starting the Blocking BlockIO operation, push to finish all non-blocking
+ // BlockIO tasks.
+ // Delay 100us to simulate the blocking time out checking.
+ //
+ OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+ while ((Task == NULL) && (!IsListEmpty (&Instance->NonBlockingTaskList))) {
+ AsyncNonBlockingTransferRoutine (NULL, Instance);
+ //
+ // Stall for 100us.
+ //
+ MicroSecondDelay (100);
+ }
+ gBS->RestoreTPL (OldTpl);
+
+ if ((Task == NULL) || ((Task != NULL) && (!Task->IsStart))) {
+ //
+ // Mark the Task to indicate that it has been started.
+ //
+ if (Task != NULL) {
+ Task->IsStart = TRUE;
+ Task->RetryTimes = (UINT32) (DivU64x32(Timeout, 1000) + 1);
+ }
+
+ if (Task != NULL) {
+ Task->Map = NULL;
+ }
+ //
+ // Package read needed
+ //
+ AhciBuildCommandFis (&CFis, AtaCommandBlock);
+
+ ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
+
+ CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
+ CmdList.AhciCmdW = Read ? 0 : 1;
+
+ AhciBuildCommand (
+ Base,
+ AhciRegisters,
+ Port,
+ PortMultiplier,
+ &CFis,
+ &CmdList,
+ AtapiCommand,
+ AtapiCommandLength,
+ 0,
+ (VOID *)MemoryAddr,
+ DataCount
+ );
+
+ Status = AhciStartCommand (
+ Base,
+ Port,
+ 0,
+ Timeout
+ );
+ if (EFI_ERROR (Status)) {
+ goto Exit;
+ }
+ }
+
+ //
+ // Wait for command compelte
+ //
+ FisBaseAddr = (UINT64)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
+ Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
+ if (Task != NULL) {
+ //
+ // For Non-blocking
+ //
+ Status = AhciCheckMemSet (
+ Offset,
+ EFI_AHCI_FIS_TYPE_MASK,
+ EFI_AHCI_FIS_REGISTER_D2H,
+ (UINTN *) (&Task->RetryTimes)
+ );
+ } else {
+ Status = AhciWaitMemSet (
+ Offset,
+ EFI_AHCI_FIS_TYPE_MASK,
+ EFI_AHCI_FIS_REGISTER_D2H,
+ Timeout
+ );
+ }
+
+ if (EFI_ERROR (Status)) {
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
+ goto Exit;
+ }
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
+ PortTfd = AhciReadReg (Base, (UINT32) Offset);
+ if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
+ Status = EFI_DEVICE_ERROR;
+ }
+
+Exit:
+ //
+ // For Blocking mode, the command should be stopped, the Fis should be disabled
+ // and the PciIo should be unmapped.
+ // For non-blocking mode, only when a error is happened (if the return status is
+ // EFI_NOT_READY that means the command doesn't finished, try again.), first do the
+ // context cleanup, then set the packet's Asb status.
+ //
+ if (Task == NULL ||
+ ((Task != NULL) && (Status != EFI_NOT_READY))
+ ) {
+ AhciStopCommand (
+ Base,
+ Port,
+ Timeout
+ );
+
+ AhciDisableFisReceive (
+ Base,
+ Port,
+ Timeout
+ );
+
+ if (Task != NULL) {
+ Task->Packet->Asb->AtaStatus = 0x01;
+ }
+ }
+
+ AhciDumpPortStatus (Base, Port, AtaStatusBlock);
+ return Status;
+}
+
+/**
+ Start a non data transfer on specific port.
+
+ @param[in] Base Base address.
+ @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
+ @param[in] Port The number of port.
+ @param[in] PortMultiplier The timeout value of stop.
+ @param[in] AtapiCommand The atapi command will be used for the
+ transfer.
+ @param[in] AtapiCommandLength The length of the atapi command.
+ @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.
+ @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
+ @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
+ @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
+ used by non-blocking mode.
+
+ @retval EFI_DEVICE_ERROR The non data transfer abort with error occurs.
+ @retval EFI_TIMEOUT The operation is time out.
+ @retval EFI_UNSUPPORTED The device is not ready for transfer.
+ @retval EFI_SUCCESS The non data transfer executes successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciNonDataTransfer (
+ IN VOID *Base,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
+ IN UINT8 AtapiCommandLength,
+ IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
+ IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
+ IN UINT64 Timeout,
+ IN ATA_NONBLOCK_TASK *Task
+ )
+{
+ EFI_STATUS Status;
+ UINT64 FisBaseAddr;
+ UINTN Offset;
+ UINT32 PortTfd;
+ EFI_AHCI_COMMAND_FIS CFis;
+ EFI_AHCI_COMMAND_LIST CmdList;
+
+ //
+ // Package read needed
+ //
+ AhciBuildCommandFis (&CFis, AtaCommandBlock);
+
+ ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
+
+ CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
+
+ AhciBuildCommand (
+ Base,
+ AhciRegisters,
+ Port,
+ PortMultiplier,
+ &CFis,
+ &CmdList,
+ AtapiCommand,
+ AtapiCommandLength,
+ 0,
+ NULL,
+ 0
+ );
+
+ Status = AhciStartCommand (
+ Base,
+ Port,
+ 0,
+ Timeout
+ );
+ if (EFI_ERROR (Status)) {
+ goto Exit;
+ }
+
+ //
+ // Wait device sends the Response Fis
+ //
+ FisBaseAddr = (UINT64)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
+ Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
+ Status = AhciWaitMemSet (
+ Offset,
+ EFI_AHCI_FIS_TYPE_MASK,
+ EFI_AHCI_FIS_REGISTER_D2H,
+ Timeout
+ );
+
+ if (EFI_ERROR (Status)) {
+ goto Exit;
+ }
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
+ PortTfd = AhciReadReg (Base, (UINT32) Offset);
+ if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
+ Status = EFI_DEVICE_ERROR;
+ }
+
+Exit:
+ AhciStopCommand (
+ Base,
+ Port,
+ Timeout
+ );
+
+ AhciDisableFisReceive (
+ Base,
+ Port,
+ Timeout
+ );
+
+ AhciDumpPortStatus (Base, Port, AtaStatusBlock);
+
+ return Status;
+}
+
+/**
+ Stop command running for giving port
+
+ @param Base Base address.
+ @param Port The number of port.
+ @param Timeout The timeout value of stop, uses 100ns as a unit.
+
+ @retval EFI_DEVICE_ERROR The command stop unsuccessfully.
+ @retval EFI_TIMEOUT The operation is time out.
+ @retval EFI_SUCCESS The command stop successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciStopCommand (
+ IN VOID *Base,
+ IN UINT8 Port,
+ IN UINT64 Timeout
+ )
+{
+ UINT32 Offset;
+ UINT32 Data;
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
+ Data = AhciReadReg (Base, Offset);
+
+ if ((Data & (EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_CR)) == 0) {
+ return EFI_SUCCESS;
+ }
+
+ if ((Data & EFI_AHCI_PORT_CMD_ST) != 0) {
+ AhciAndRegWithFlush (Base, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_ST));
+ }
+
+ return AhciWaitMmioSet (
+ Base,
+ Offset,
+ EFI_AHCI_PORT_CMD_CR,
+ 0,
+ Timeout
+ );
+}
+
+/**
+ Start command for give slot on specific port.
+
+ @param Base Base address.
+ @param Port The number of port.
+ @param CommandSlot The number of Command Slot.
+ @param Timeout The timeout value of start, uses 100ns as a unit.
+
+ @retval EFI_DEVICE_ERROR The command start unsuccessfully.
+ @retval EFI_TIMEOUT The operation is time out.
+ @retval EFI_SUCCESS The command start successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciStartCommand (
+ IN VOID *Base,
+ IN UINT8 Port,
+ IN UINT8 CommandSlot,
+ IN UINT64 Timeout
+ )
+{
+ UINT32 CmdSlotBit;
+ EFI_STATUS Status;
+ UINT32 PortStatus;
+ UINT32 StartCmd;
+ UINT32 PortTfd;
+ UINT32 Offset;
+ UINT32 Capability;
+
+ //
+ // Collect AHCI controller information
+ //
+ Capability = AhciReadReg(Base, EFI_AHCI_CAPABILITY_OFFSET);
+
+ CmdSlotBit = (UINT32) (1 << CommandSlot);
+
+ AhciClearPortStatus (
+ Base,
+ Port
+ );
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
+
+ Status = AhciEnableFisReceive (
+ Base,
+ Port,
+ Timeout
+ );
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
+ PortStatus = AhciReadReg (Base, Offset);
+
+ StartCmd = 0;
+ if ((PortStatus & EFI_AHCI_PORT_CMD_ALPE) != 0) {
+ StartCmd = AhciReadReg (Base, Offset);
+ StartCmd &= ~EFI_AHCI_PORT_CMD_ICC_MASK;
+ StartCmd |= EFI_AHCI_PORT_CMD_ACTIVE;
+ }
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
+ PortTfd = AhciReadReg (Base, Offset);
+
+ if ((PortTfd & (EFI_AHCI_PORT_TFD_BSY | EFI_AHCI_PORT_TFD_DRQ)) != 0) {
+ if ((Capability & BIT24) != 0) {
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
+ AhciOrRegWithFlush (Base, Offset, EFI_AHCI_PORT_CMD_CLO);
+
+ AhciWaitMmioSet (
+ Base,
+ Offset,
+ EFI_AHCI_PORT_CMD_CLO,
+ 0,
+ Timeout
+ );
+ }
+ }
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
+ AhciOrRegWithFlush (Base, Offset, EFI_AHCI_PORT_CMD_ST | StartCmd);
+
+ //
+ // Setting the command
+ //
+ /* We don't use NCQ so don't need to set SACT */
+ /*
+ * Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SACT;
+ * AhciAndRegWithFlush (Base, Offset, 0);
+ * AhciOrRegWithFlush (Base, Offset, CmdSlotBit);
+ */
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CI;
+ AhciAndRegWithFlush (Base, Offset, 0);
+ AhciOrRegWithFlush (Base, Offset, CmdSlotBit);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Do AHCI port reset.
+
+ @param Base Base address.
+ @param Port The number of port.
+ @param Timeout The timeout value of reset, uses 100ns as a unit.
+
+ @retval EFI_DEVICE_ERROR The port reset unsuccessfully
+ @retval EFI_TIMEOUT The reset operation is time out.
+ @retval EFI_SUCCESS The port reset successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciPortReset (
+ IN VOID *Base,
+ IN UINT8 Port,
+ IN UINT64 Timeout
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Offset;
+
+ AhciClearPortStatus (Base, Port);
+
+ AhciStopCommand (Base, Port, Timeout);
+
+ AhciDisableFisReceive (Base, Port, Timeout);
+
+ AhciEnableFisReceive (Base, Port, Timeout);
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SCTL;
+
+ AhciOrRegWithFlush (Base, Offset, EFI_AHCI_PORT_SCTL_DET_INIT);
+
+ //
+ // wait 5 millisecond before de-assert DET
+ //
+ MicroSecondDelay (5000);
+
+ AhciAndRegWithFlush (Base, Offset, (UINT32)EFI_AHCI_PORT_SCTL_MASK);
+
+ //
+ // wait 5 millisecond before de-assert DET
+ //
+ MicroSecondDelay (5000);
+
+ //
+ // Wait for communication to be re-established
+ //
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
+ Status = AhciWaitMmioSet (
+ Base,
+ Offset,
+ EFI_AHCI_PORT_SSTS_DET_MASK,
+ EFI_AHCI_PORT_SSTS_DET_PCE,
+ Timeout
+ );
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
+ AhciOrRegWithFlush (Base, Offset, EFI_AHCI_PORT_ERR_CLEAR);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Do AHCI HBA reset.
+
+ @param Base Base address.
+ @param Timeout The timeout value of reset, uses 100ns as a unit.
+
+ @retval EFI_DEVICE_ERROR AHCI controller is failed to complete hardware reset.
+ @retval EFI_TIMEOUT The reset operation is time out.
+ @retval EFI_SUCCESS AHCI controller is reset successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciReset (
+ IN VOID *Base,
+ IN UINT64 Timeout
+ )
+{
+ UINT32 Delay;
+ UINT32 Value;
+
+ AhciOrRegWithFlush (Base, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);
+
+ Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
+
+ do {
+ Value = AhciReadReg(Base, EFI_AHCI_GHC_OFFSET);
+
+ if ((Value & EFI_AHCI_GHC_RESET) == 0) {
+ break;
+ }
+
+ //
+ // Stall for 100 microseconds.
+ //
+ MicroSecondDelay(100);
+
+ Delay--;
+ } while (Delay > 0);
+
+ if (Delay == 0) {
+ return EFI_TIMEOUT;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Send SMART Return Status command to check if the execution of SMART cmd is successful or not.
+
+ @param Base Base address.
+ @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
+ @param Port The number of port.
+ @param PortMultiplier The timeout value of stop.
+ @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
+
+ @retval EFI_SUCCESS Successfully get the return status of S.M.A.R.T command execution.
+ @retval Others Fail to get return status data.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciAtaSmartReturnStatusCheck (
+ IN VOID *Base,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
+ )
+{
+ EFI_STATUS Status;
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
+ UINT8 LBAMid;
+ UINT8 LBAHigh;
+ UINT64 FisBaseAddr;
+ UINT32 Value;
+
+ ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
+
+ AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
+ AtaCommandBlock.AtaFeatures = ATA_SMART_RETURN_STATUS;
+ AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
+ AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
+
+ //
+ // Send S.M.A.R.T Read Return Status command to device
+ //
+ Status = AhciNonDataTransfer (
+ Base,
+ AhciRegisters,
+ (UINT8)Port,
+ (UINT8)PortMultiplier,
+ NULL,
+ 0,
+ &AtaCommandBlock,
+ AtaStatusBlock,
+ ATA_ATAPI_TIMEOUT,
+ NULL
+ );
+
+ if (EFI_ERROR (Status)) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ FisBaseAddr = (UINT64)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
+
+ Value = *(UINT32 *) (FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET);
+
+ if ((Value & EFI_AHCI_FIS_TYPE_MASK) == EFI_AHCI_FIS_REGISTER_D2H) {
+ LBAMid = ((UINT8 *)(UINT64)(FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET))[5];
+ LBAHigh = ((UINT8 *)(UINT64)(FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET))[6];
+
+ if ((LBAMid == 0x4f) && (LBAHigh == 0xc2)) {
+ //
+ // The threshold exceeded condition is not detected by the device
+ //
+ DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is not detected\n"));
+
+ } else if ((LBAMid == 0xf4) && (LBAHigh == 0x2c)) {
+ //
+ // The threshold exceeded condition is detected by the device
+ //
+ DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is detected\n"));
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Enable SMART command of the disk if supported.
+
+ @param Base Base address.
+ @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
+ @param Port The number of port.
+ @param PortMultiplier The timeout value of stop.
+ @param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.
+ @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
+
+**/
+VOID
+EFIAPI
+AhciAtaSmartSupport (
+ IN VOID *Base,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN EFI_IDENTIFY_DATA *IdentifyData,
+ IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
+ )
+{
+ EFI_STATUS Status;
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
+
+ //
+ // Detect if the device supports S.M.A.R.T.
+ //
+ if ((IdentifyData->AtaData.command_set_supported_82 & 0x0001) != 0x0001) {
+ //
+ // S.M.A.R.T is not supported by the device
+ //
+ DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at port [%d] PortMultiplier [%d]!\n",
+ Port, PortMultiplier));
+ } else {
+ //
+ // Check if the feature is enabled. If not, then enable S.M.A.R.T.
+ //
+ if ((IdentifyData->AtaData.command_set_feature_enb_85 & 0x0001) != 0x0001) {
+ ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
+
+ AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
+ AtaCommandBlock.AtaFeatures = ATA_SMART_ENABLE_OPERATION;
+ AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
+ AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
+
+ //
+ // Send S.M.A.R.T Enable command to device
+ //
+ Status = AhciNonDataTransfer (
+ Base,
+ AhciRegisters,
+ (UINT8)Port,
+ (UINT8)PortMultiplier,
+ NULL,
+ 0,
+ &AtaCommandBlock,
+ AtaStatusBlock,
+ ATA_ATAPI_TIMEOUT,
+ NULL
+ );
+
+
+ if (!EFI_ERROR (Status)) {
+ //
+ // Send S.M.A.R.T AutoSave command to device
+ //
+ ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
+
+ AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
+ AtaCommandBlock.AtaFeatures = 0xD2;
+ AtaCommandBlock.AtaSectorCount = 0xF1;
+ AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
+ AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
+
+ Status = AhciNonDataTransfer (
+ Base,
+ AhciRegisters,
+ (UINT8)Port,
+ (UINT8)PortMultiplier,
+ NULL,
+ 0,
+ &AtaCommandBlock,
+ AtaStatusBlock,
+ ATA_ATAPI_TIMEOUT,
+ NULL
+ );
+
+ if (!EFI_ERROR (Status)) {
+ Status = AhciAtaSmartReturnStatusCheck (
+ Base,
+ AhciRegisters,
+ (UINT8)Port,
+ (UINT8)PortMultiplier,
+ AtaStatusBlock
+ );
+ }
+ }
+ }
+ DEBUG ((EFI_D_INFO, "Enabled S.M.A.R.T feature at port [%d] PortMultiplier [%d]!\n",
+ Port, PortMultiplier));
+ }
+
+ return ;
+}
+
+/**
+ Send Buffer cmd to specific device.
+
+ @param Base Base address.
+ @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
+ @param Port The number of port.
+ @param PortMultiplier The timeout value of stop.
+ @param Buffer The data buffer to store IDENTIFY PACKET data.
+
+ @retval EFI_DEVICE_ERROR The cmd abort with error occurs.
+ @retval EFI_TIMEOUT The operation is time out.
+ @retval EFI_UNSUPPORTED The device is not ready for executing.
+ @retval EFI_SUCCESS The cmd executes successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciIdentify (
+ IN VOID *Base,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN OUT EFI_IDENTIFY_DATA *Buffer
+ )
+{
+ EFI_STATUS Status;
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
+ EFI_ATA_STATUS_BLOCK AtaStatusBlock;
+
+ if (Base == NULL || AhciRegisters == NULL || Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
+ ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
+
+ AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DRIVE;
+ AtaCommandBlock.AtaSectorCount = 1;
+
+ Status = AhciPioTransfer (
+ Base,
+ AhciRegisters,
+ Port,
+ PortMultiplier,
+ NULL,
+ 0,
+ TRUE,
+ &AtaCommandBlock,
+ &AtaStatusBlock,
+ Buffer,
+ sizeof (EFI_IDENTIFY_DATA),
+ ATA_ATAPI_TIMEOUT,
+ NULL
+ );
+
+ return Status;
+}
+
+/**
+ Send Buffer cmd to specific device.
+
+ @param Base Base address.
+ @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
+ @param Port The number of port.
+ @param PortMultiplier The timeout value of stop.
+ @param Buffer The data buffer to store IDENTIFY PACKET data.
+
+ @retval EFI_DEVICE_ERROR The cmd abort with error occurs.
+ @retval EFI_TIMEOUT The operation is time out.
+ @retval EFI_UNSUPPORTED The device is not ready for executing.
+ @retval EFI_SUCCESS The cmd executes successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciIdentifyPacket (
+ IN VOID *Base,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN OUT EFI_IDENTIFY_DATA *Buffer
+ )
+{
+ EFI_STATUS Status;
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
+ EFI_ATA_STATUS_BLOCK AtaStatusBlock;
+
+ if (Base == NULL || AhciRegisters == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
+ ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
+
+ AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DEVICE;
+ AtaCommandBlock.AtaSectorCount = 1;
+
+ Status = AhciPioTransfer (
+ Base,
+ AhciRegisters,
+ Port,
+ PortMultiplier,
+ NULL,
+ 0,
+ TRUE,
+ &AtaCommandBlock,
+ &AtaStatusBlock,
+ Buffer,
+ sizeof (EFI_IDENTIFY_DATA),
+ ATA_ATAPI_TIMEOUT,
+ NULL
+ );
+
+ return Status;
+}
+
+/**
+ Send SET FEATURE cmd on specific device.
+
+ @param Base Base address.
+ @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
+ @param Port The number of port.
+ @param PortMultiplier The timeout value of stop.
+ @param Feature The data to send Feature register.
+ @param FeatureSpecificData The specific data for SET FEATURE cmd.
+
+ @retval EFI_DEVICE_ERROR The cmd abort with error occurs.
+ @retval EFI_TIMEOUT The operation is time out.
+ @retval EFI_UNSUPPORTED The device is not ready for executing.
+ @retval EFI_SUCCESS The cmd executes successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciDeviceSetFeature (
+ IN VOID *Base,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN UINT16 Feature,
+ IN UINT32 FeatureSpecificData
+ )
+{
+ EFI_STATUS Status;
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
+ EFI_ATA_STATUS_BLOCK AtaStatusBlock;
+
+ ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
+ ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
+
+ AtaCommandBlock.AtaCommand = ATA_CMD_SET_FEATURES;
+ AtaCommandBlock.AtaFeatures = (UINT8) Feature;
+ AtaCommandBlock.AtaFeaturesExp = (UINT8) (Feature >> 8);
+ AtaCommandBlock.AtaSectorCount = (UINT8) FeatureSpecificData;
+ AtaCommandBlock.AtaSectorNumber = (UINT8) (FeatureSpecificData >> 8);
+ AtaCommandBlock.AtaCylinderLow = (UINT8) (FeatureSpecificData >> 16);
+ AtaCommandBlock.AtaCylinderHigh = (UINT8) (FeatureSpecificData >> 24);
+
+ Status = AhciNonDataTransfer (
+ Base,
+ AhciRegisters,
+ (UINT8)Port,
+ (UINT8)PortMultiplier,
+ NULL,
+ 0,
+ &AtaCommandBlock,
+ &AtaStatusBlock,
+ ATA_ATAPI_TIMEOUT,
+ NULL
+ );
+
+ return Status;
+}
+
+/**
+ This function is used to send out ATAPI commands conforms to the Packet Command
+ with PIO Protocol.
+
+ @param Base Base address.
+ @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
+ @param Port The number of port.
+ @param PortMultiplier The number of port multiplier.
+ @param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
+
+ @retval EFI_SUCCESS send out the ATAPI packet command successfully
+ and device sends data successfully.
+ @retval EFI_DEVICE_ERROR the device failed to send data.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciPacketCommandExecute (
+ IN VOID *Base,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet
+ )
+{
+ EFI_STATUS Status;
+ VOID *Buffer;
+ UINT32 Length;
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
+ EFI_ATA_STATUS_BLOCK AtaStatusBlock;
+ BOOLEAN Read;
+
+ if (Packet == NULL || Packet->Cdb == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
+ ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
+ AtaCommandBlock.AtaCommand = ATA_CMD_PACKET;
+ //
+ // No OVL; No DMA
+ //
+ AtaCommandBlock.AtaFeatures = 0x00;
+ //
+ // set the transfersize to ATAPI_MAX_BYTE_COUNT to let the device
+ // determine how many data should be transferred.
+ //
+ AtaCommandBlock.AtaCylinderLow = (UINT8) (ATAPI_MAX_BYTE_COUNT & 0x00ff);
+ AtaCommandBlock.AtaCylinderHigh = (UINT8) (ATAPI_MAX_BYTE_COUNT >> 8);
+
+ if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_READ) {
+ Buffer = Packet->InDataBuffer;
+ Length = Packet->InTransferLength;
+ Read = TRUE;
+ } else {
+ Buffer = Packet->OutDataBuffer;
+ Length = Packet->OutTransferLength;
+ Read = FALSE;
+ }
+
+ if (Length == 0) {
+ Status = AhciNonDataTransfer (
+ Base,
+ AhciRegisters,
+ Port,
+ PortMultiplier,
+ Packet->Cdb,
+ Packet->CdbLength,
+ &AtaCommandBlock,
+ &AtaStatusBlock,
+ Packet->Timeout,
+ NULL
+ );
+ } else {
+ Status = AhciPioTransfer (
+ Base,
+ AhciRegisters,
+ Port,
+ PortMultiplier,
+ Packet->Cdb,
+ Packet->CdbLength,
+ Read,
+ &AtaCommandBlock,
+ &AtaStatusBlock,
+ Buffer,
+ Length,
+ Packet->Timeout,
+ NULL
+ );
+ }
+ return Status;
+}
+
+/**
+ Allocate transfer-related data struct which is used at AHCI mode.
+
+ @param Base Base address.
+ @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciCreateTransferDescriptor (
+ IN VOID *Base,
+ IN OUT EFI_AHCI_REGISTERS *AhciRegisters
+ )
+{
+ EFI_STATUS Status;
+ VOID *Buffer;
+ UINT32 Capability;
+ UINT8 MaxPortNumber;
+ UINT8 MaxCommandSlotNumber;
+ UINT64 MaxReceiveFisSize;
+ UINT64 MaxCommandListSize;
+ UINT64 MaxCommandTableSize;
+ //
+ // Collect AHCI controller information
+ //
+ Capability = AhciReadReg(Base, EFI_AHCI_CAPABILITY_OFFSET);
+ MaxPortNumber = (UINT8) ((Capability & 0x1F) + 1);
+ //
+ // Get the number of command slots per port supported by this HBA.
+ //
+ MaxCommandSlotNumber = (UINT8) (((Capability & 0x1F00) >> 8) + 1);
+
+ MaxReceiveFisSize = MaxPortNumber * sizeof (EFI_AHCI_RECEIVED_FIS);
+ Buffer = AllocateZeroPool((UINTN) MaxReceiveFisSize + 256);
+
+ if (!Buffer) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ AhciRegisters->AhciRFis = Buffer;
+ AhciRegisters->MaxReceiveFisSize = MaxReceiveFisSize;
+
+
+ //
+ // Allocate memory for command list
+ // Note that the implemenation is a single task model which only use a command list for all ports.
+ //
+ MaxCommandListSize = MaxCommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST);
+ Buffer = AllocateZeroPool((UINTN) MaxCommandListSize + 2048);
+
+ if (!Buffer) {
+ return EFI_OUT_OF_RESOURCES;
+ goto Error2;
+ }
+
+ AhciRegisters->AhciCmdList = Buffer;
+ AhciRegisters->MaxCommandListSize = MaxCommandListSize;
+
+ //
+ // Allocate memory for command table
+ // According to AHCI 1.3 spec, a PRD table can contain maximum 65535 entries.
+ //
+ MaxCommandTableSize = sizeof (EFI_AHCI_COMMAND_TABLE);
+
+
+ Buffer = AllocateZeroPool((UINTN) MaxCommandTableSize + 256);
+
+ if (!Buffer) {
+ //
+ // Free mapped resource.
+ //
+ Status = EFI_OUT_OF_RESOURCES;
+ goto Error1;
+ }
+
+ AhciRegisters->AhciCommandTable = Buffer;
+ AhciRegisters->MaxCommandTableSize = MaxCommandTableSize;
+
+ AhciRegisters->AhciCmdList = (VOID *) (((UINT64)AhciRegisters->AhciCmdList + 2048) & (~(2048 - 1)));
+ AhciRegisters->AhciRFis = (VOID *) (((UINT64)AhciRegisters->AhciRFis + 256) & (~(256 - 1)));
+ AhciRegisters->AhciCommandTable = (VOID *) (((UINT64)AhciRegisters->AhciCommandTable + 256) & (~(256 - 1)));
+
+ return EFI_SUCCESS;
+ //
+ // Map error or unable to map the whole CmdList buffer into a contiguous region.
+ //
+Error1:
+ FreePool (AhciRegisters->AhciCmdList);
+Error2:
+ FreePool (AhciRegisters->AhciRFis);
+
+ return Status;
+}
+
+/**
+ Initialize ATA host controller at AHCI mode.
+
+ The function is designed to initialize ATA host controller.
+
+ @param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciModeInitialization (
+ IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance
+ )
+{
+ EFI_STATUS Status;
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
+ UINT32 Capability;
+ UINT8 MaxPortNumber;
+ UINT32 PortImplementBitMap;
+ UINT64 BaseAddress;
+ EFI_AHCI_REGISTERS *AhciRegisters;
+
+ UINT8 Port;
+ DATA_64 Data64;
+ UINT32 Offset;
+ UINT32 Data;
+ EFI_IDENTIFY_DATA Buffer;
+ EFI_ATA_DEVICE_TYPE DeviceType;
+ EFI_ATA_COLLECTIVE_MODE *SupportedModes;
+ EFI_ATA_TRANSFER_MODE TransferMode;
+ UINT32 PhyDetectDelay;
+
+ if (Instance == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ IdeInit = Instance->IdeControllerInit;
+
+ if (Instance->Mode != EfiAtaAhciMode) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ /* Support memory-mapped base address */
+ IdeInit->GetMappedBaseAddress(IdeInit, &BaseAddress);
+ Instance->AhciRegisters.MapBaseAddress = (VOID *) BaseAddress;
+
+ if (!Instance->AhciRegisters.MapBaseAddress) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = AhciReset (Instance->AhciRegisters.MapBaseAddress, EFI_AHCI_BUS_RESET_TIMEOUT);
+
+ if (EFI_ERROR (Status)) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // Enable AE before accessing any AHCI registers
+ //
+ AhciOrRegWithFlush (Instance->AhciRegisters.MapBaseAddress, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
+
+ //
+ // Collect AHCI controller information
+ //
+ Capability = AhciReadReg(Instance->AhciRegisters.MapBaseAddress, EFI_AHCI_CAPABILITY_OFFSET);
+
+ //
+ // Get the number of command slots per port supported by this HBA.
+ //
+ MaxPortNumber = (UINT8) ((Capability & 0x1F) + 1);
+
+ //
+ // Get the bit map of those ports exposed by this HBA.
+ // It indicates which ports that the HBA supports are available for software to use.
+ //
+ PortImplementBitMap = AhciReadReg(Instance->AhciRegisters.MapBaseAddress, EFI_AHCI_PI_OFFSET);
+
+ DEBUG ((EFI_D_INFO, "PortImplementBitMap:%x\n", PortImplementBitMap));
+
+ AhciRegisters = &Instance->AhciRegisters;
+ Status = AhciCreateTransferDescriptor (Instance->AhciRegisters.MapBaseAddress, AhciRegisters);
+
+ if (EFI_ERROR (Status)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ for (Port = 0; Port < MaxPortNumber; Port ++) {
+ if ((PortImplementBitMap & (BIT0 << Port)) != 0) {
+ IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelEnumeration, Port);
+
+ //
+ // Initialize FIS Base Address Register and Command List Base Address Register for use.
+ //
+ Data64.Uint64 = (UINT64) (AhciRegisters->AhciRFis) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_FB;
+ AhciWriteRegWithFlush (Instance->AhciRegisters.MapBaseAddress, Offset, Data64.Uint32.Lower32);
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_FBU;
+ AhciWriteRegWithFlush (Instance->AhciRegisters.MapBaseAddress, Offset, Data64.Uint32.Upper32);
+
+ Data64.Uint64 = (UINT64) (AhciRegisters->AhciCmdList);
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CLB;
+ AhciWriteRegWithFlush (Instance->AhciRegisters.MapBaseAddress, Offset, Data64.Uint32.Lower32);
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CLBU;
+ AhciWriteRegWithFlush (Instance->AhciRegisters.MapBaseAddress, Offset, Data64.Uint32.Upper32);
+
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
+ Data = AhciReadReg (Instance->AhciRegisters.MapBaseAddress, Offset);
+ if ((Data & EFI_AHCI_PORT_CMD_CPD) != 0) {
+ AhciOrRegWithFlush (Instance->AhciRegisters.MapBaseAddress, Offset, EFI_AHCI_PORT_CMD_POD);
+ }
+
+ if ((Capability & EFI_AHCI_CAP_SSS) != 0) {
+ DEBUG ((EFI_D_INFO, "Port :%d spinned up\n", Port));
+ AhciOrRegWithFlush (Instance->AhciRegisters.MapBaseAddress, Offset, EFI_AHCI_PORT_CMD_SUD);
+ }
+
+ //
+ // Disable aggressive power management.
+ //
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SCTL;
+ AhciOrRegWithFlush (Instance->AhciRegisters.MapBaseAddress, Offset, EFI_AHCI_PORT_SCTL_IPM_INIT);
+
+ //
+ // Disable the reporting of the corresponding interrupt to system software.
+ //
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IE;
+ AhciOrRegWithFlush (Instance->AhciRegisters.MapBaseAddress, Offset, 0);
+
+ //
+ // Now inform the IDE Controller Init Module.
+ //
+ IdeInit->NotifyPhase (IdeInit, EfiIdeBusBeforeDevicePresenceDetection, Port);
+
+ //
+ // Enable FIS Receive DMA engine for the first D2H FIS and spin up.
+ //
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
+ AhciOrRegWithFlush (Instance->AhciRegisters.MapBaseAddress, Offset, EFI_AHCI_PORT_CMD_FRE);
+
+
+ //
+ // Wait no longer than 10 ms to wait the Phy to detect the presence of a device.
+ // It's the requirment from SATA1.0a spec section 5.2.
+ //
+ PhyDetectDelay = EFI_AHCI_BUS_PHY_DETECT_TIMEOUT;
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
+ do {
+ Data = AhciReadReg (Instance->AhciRegisters.MapBaseAddress, Offset) & EFI_AHCI_PORT_SSTS_DET_MASK;
+ if ((Data == EFI_AHCI_PORT_SSTS_DET_PCE) || (Data == EFI_AHCI_PORT_SSTS_DET)) {
+ break;
+ }
+
+ MicroSecondDelay (1000);
+ PhyDetectDelay--;
+ } while (PhyDetectDelay > 0);
+
+ if (PhyDetectDelay == 0) {
+ //
+ // No device detected at this port.
+ //
+ DEBUG ((EFI_D_INFO, "No device detected at this port:%p\n", Port));
+ continue;
+ }
+
+ //
+ // According to SATA1.0a spec section 5.2, we need to wait for PxTFD.BSY and PxTFD.DRQ
+ // and PxTFD.ERR to be zero. The maximum wait time is 16s which is defined at ATA spec.
+ //
+ PhyDetectDelay = 16 * 1000;
+ do {
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
+ if (AhciReadReg(Instance->AhciRegisters.MapBaseAddress, Offset) != 0) {
+ AhciWriteRegWithFlush (Instance->AhciRegisters.MapBaseAddress, Offset,
+ AhciReadReg(Instance->AhciRegisters.MapBaseAddress, Offset));
+ }
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
+
+ Data = AhciReadReg (Instance->AhciRegisters.MapBaseAddress, Offset) & EFI_AHCI_PORT_TFD_MASK;
+ if (Data == 0) {
+ break;
+ }
+
+ MicroSecondDelay (1000);
+ PhyDetectDelay--;
+ } while (PhyDetectDelay > 0);
+
+ if (PhyDetectDelay == 0) {
+ DEBUG ((EFI_D_INFO, "No device detected at this port:%p\n", Port));
+ continue;
+ }
+
+ Data = AhciReadReg (Instance->AhciRegisters.MapBaseAddress, Offset);
+
+ //
+ // When the first D2H register FIS is received, the content of PxSIG register is updated.
+ //
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SIG;
+ Status = AhciWaitMmioSet (
+ Instance->AhciRegisters.MapBaseAddress,
+ Offset,
+ 0x0000FFFF,
+ 0x00000101,
+ EFI_TIMER_PERIOD_SECONDS(16)
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_INFO, "Wait PORT_SIG timeout\n"));
+ continue;
+ }
+
+ Data = AhciReadReg (Instance->AhciRegisters.MapBaseAddress, Offset);
+
+ if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == EFI_AHCI_ATAPI_DEVICE_SIG) {
+ Status = AhciIdentifyPacket (Instance->AhciRegisters.MapBaseAddress, AhciRegisters, Port, 0, &Buffer);
+
+ if (EFI_ERROR (Status)) {
+ continue;
+ }
+
+ DeviceType = EfiIdeCdrom;
+ } else if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == EFI_AHCI_ATA_DEVICE_SIG) {
+ Status = AhciIdentify (Instance->AhciRegisters.MapBaseAddress, AhciRegisters, Port, 0, &Buffer);
+
+ if (EFI_ERROR (Status)) {
+ REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED));
+ continue;
+ }
+
+ DeviceType = EfiIdeHarddisk;
+ } else {
+ continue;
+ }
+ DEBUG ((EFI_D_INFO, "port [%d] port mulitplier [%d] has a [%a]\n",
+ Port, 0, DeviceType == EfiIdeCdrom ? "cdrom" : "harddisk"));
+
+ //
+ // If the device is a hard disk, then try to enable S.M.A.R.T feature
+ //
+ if (DeviceType == EfiIdeHarddisk) {
+ AhciAtaSmartSupport (
+ Instance->AhciRegisters.MapBaseAddress,
+ AhciRegisters,
+ Port,
+ 0,
+ &Buffer,
+ NULL
+ );
+ }
+
+ //
+ // Submit identify data to IDE controller init driver
+ //
+ IdeInit->SubmitData (IdeInit, Port, 0, &Buffer);
+
+ //
+ // Now start to config ide device parameter and transfer mode.
+ //
+ Status = IdeInit->CalculateMode (
+ IdeInit,
+ Port,
+ 0,
+ &SupportedModes
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Calculate Mode Fail, Status = %r\n", Status));
+ continue;
+ }
+
+ //
+ // Set best supported PIO mode on this IDE device
+ //
+ if (SupportedModes->PioMode.Mode <= EfiAtaPioMode2) {
+ TransferMode.ModeCategory = EFI_ATA_MODE_DEFAULT_PIO;
+ } else {
+ TransferMode.ModeCategory = EFI_ATA_MODE_FLOW_PIO;
+ }
+
+ TransferMode.ModeNumber = (UINT8) (SupportedModes->PioMode.Mode);
+
+#ifdef APM_XGENE
+ SupportedModes->UdmaMode.Valid = FALSE;
+#endif
+
+ //
+ // Set supported DMA mode on this IDE device. Note that UDMA & MDMA cann't
+ // be set together. Only one DMA mode can be set to a device. If setting
+ // DMA mode operation fails, we can continue moving on because we only use
+ // PIO mode at boot time. DMA modes are used by certain kind of OS booting
+ //
+ if (SupportedModes->UdmaMode.Valid) {
+ TransferMode.ModeCategory = EFI_ATA_MODE_UDMA;
+ TransferMode.ModeNumber = (UINT8) (SupportedModes->UdmaMode.Mode);
+ } else if (SupportedModes->MultiWordDmaMode.Valid) {
+ TransferMode.ModeCategory = EFI_ATA_MODE_MDMA;
+ TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;
+ }
+
+ Status = AhciDeviceSetFeature (Instance->AhciRegisters.MapBaseAddress, AhciRegisters,
+ Port, 0, 0x03, (UINT32)(*(UINT8 *)&TransferMode));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
+ continue;
+ }
+
+ //
+ // Found a ATA or ATAPI device, add it into the device list.
+ //
+ CreateNewDeviceInfo (Instance, Port, 0, DeviceType, &Buffer);
+ if (DeviceType == EfiIdeHarddisk) {
+ REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_PC_ENABLE));
+ }
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/AhciMode.h b/Platforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/AhciMode.h
new file mode 100755
index 0000000..4b2cc5b
--- /dev/null
+++ b/Platforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/AhciMode.h
@@ -0,0 +1,381 @@
+/** @file
+ Header file for AHCI mode of ATA host controller.
+
+ Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __ATA_HC_AHCI_MODE_H__
+#define __ATA_HC_AHCI_MODE_H__
+
+#define EFI_AHCI_CAPABILITY_OFFSET 0x0000
+#define EFI_AHCI_CAP_SSS BIT27
+#define EFI_AHCI_CAP_S64A BIT31
+#define EFI_AHCI_GHC_OFFSET 0x0004
+#define EFI_AHCI_GHC_RESET BIT0
+#define EFI_AHCI_GHC_IE BIT1
+#define EFI_AHCI_GHC_ENABLE BIT31
+#define EFI_AHCI_IS_OFFSET 0x0008
+#define EFI_AHCI_PI_OFFSET 0x000C
+
+typedef struct {
+ UINT32 Lower32;
+ UINT32 Upper32;
+} DATA_32;
+
+typedef union {
+ DATA_32 Uint32;
+ UINT64 Uint64;
+} DATA_64;
+
+///
+/// PIO mode definition
+///
+typedef enum {
+ EfiAtaPioModeBelow2,
+ EfiAtaPioMode2,
+ EfiAtaPioMode3,
+ EfiAtaPioMode4
+} EFI_ATA_PIO_MODE;
+
+//
+// IDE transfer mode
+//
+#define EFI_ATA_MODE_DEFAULT_PIO 0x00
+#define EFI_ATA_MODE_FLOW_PIO 0x01
+#define EFI_ATA_MODE_MDMA 0x04
+#define EFI_ATA_MODE_UDMA 0x08
+
+//
+// Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.
+//
+#define EFI_AHCI_BUS_PHY_DETECT_TIMEOUT 10
+//
+// Refer SATA1.0a spec, the FIS enable time should be less than 500ms.
+//
+#define EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT EFI_TIMER_PERIOD_MILLISECONDS(500)
+//
+// Refer SATA1.0a spec, the bus reset time should be less than 1s.
+//
+#define EFI_AHCI_BUS_RESET_TIMEOUT EFI_TIMER_PERIOD_SECONDS(1)
+
+#define EFI_AHCI_ATAPI_DEVICE_SIG 0xEB140000
+#define EFI_AHCI_ATA_DEVICE_SIG 0x00000000
+#define EFI_AHCI_PORT_MULTIPLIER_SIG 0x96690000
+#define EFI_AHCI_ATAPI_SIG_MASK 0xFFFF0000
+
+//
+// Each PRDT entry can point to a memory block up to 4M byte
+//
+#define EFI_AHCI_MAX_DATA_PER_PRDT 0x400000
+
+#define EFI_AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device
+#define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20
+#define EFI_AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host
+#define EFI_AHCI_FIS_REGISTER_D2H_LENGTH 20
+#define EFI_AHCI_FIS_DMA_ACTIVATE 0x39 //DMA Activate FIS - Device to Host
+#define EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH 4
+#define EFI_AHCI_FIS_DMA_SETUP 0x41 //DMA Setup FIS - Bi-directional
+#define EFI_AHCI_FIS_DMA_SETUP_LENGTH 28
+#define EFI_AHCI_FIS_DATA 0x46 //Data FIS - Bi-directional
+#define EFI_AHCI_FIS_BIST 0x58 //BIST Activate FIS - Bi-directional
+#define EFI_AHCI_FIS_BIST_LENGTH 12
+#define EFI_AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host
+#define EFI_AHCI_FIS_PIO_SETUP_LENGTH 20
+#define EFI_AHCI_FIS_SET_DEVICE 0xA1 //Set Device Bits FIS - Device to Host
+#define EFI_AHCI_FIS_SET_DEVICE_LENGTH 8
+
+#define EFI_AHCI_D2H_FIS_OFFSET 0x40
+#define EFI_AHCI_DMA_FIS_OFFSET 0x00
+#define EFI_AHCI_PIO_FIS_OFFSET 0x20
+#define EFI_AHCI_SDB_FIS_OFFSET 0x58
+#define EFI_AHCI_FIS_TYPE_MASK 0xFF
+#define EFI_AHCI_U_FIS_OFFSET 0x60
+
+//
+// Port register
+//
+#define EFI_AHCI_PORT_START 0x0100
+#define EFI_AHCI_PORT_REG_WIDTH 0x0080
+#define EFI_AHCI_PORT_CLB 0x0000
+#define EFI_AHCI_PORT_CLBU 0x0004
+#define EFI_AHCI_PORT_FB 0x0008
+#define EFI_AHCI_PORT_FBU 0x000C
+#define EFI_AHCI_PORT_IS 0x0010
+#define EFI_AHCI_PORT_IS_DHRS BIT0
+#define EFI_AHCI_PORT_IS_PSS BIT1
+#define EFI_AHCI_PORT_IS_SSS BIT2
+#define EFI_AHCI_PORT_IS_SDBS BIT3
+#define EFI_AHCI_PORT_IS_UFS BIT4
+#define EFI_AHCI_PORT_IS_DPS BIT5
+#define EFI_AHCI_PORT_IS_PCS BIT6
+#define EFI_AHCI_PORT_IS_DIS BIT7
+#define EFI_AHCI_PORT_IS_PRCS BIT22
+#define EFI_AHCI_PORT_IS_IPMS BIT23
+#define EFI_AHCI_PORT_IS_OFS BIT24
+#define EFI_AHCI_PORT_IS_INFS BIT26
+#define EFI_AHCI_PORT_IS_IFS BIT27
+#define EFI_AHCI_PORT_IS_HBDS BIT28
+#define EFI_AHCI_PORT_IS_HBFS BIT29
+#define EFI_AHCI_PORT_IS_TFES BIT30
+#define EFI_AHCI_PORT_IS_CPDS BIT31
+#define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF
+#define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F
+
+#define EFI_AHCI_PORT_IE 0x0014
+#define EFI_AHCI_PORT_CMD 0x0018
+#define EFI_AHCI_PORT_CMD_ST_MASK 0xFFFFFFFE
+#define EFI_AHCI_PORT_CMD_ST BIT0
+#define EFI_AHCI_PORT_CMD_SUD BIT1
+#define EFI_AHCI_PORT_CMD_POD BIT2
+#define EFI_AHCI_PORT_CMD_CLO BIT3
+#define EFI_AHCI_PORT_CMD_CR BIT15
+#define EFI_AHCI_PORT_CMD_FRE BIT4
+#define EFI_AHCI_PORT_CMD_FR BIT14
+#define EFI_AHCI_PORT_CMD_MASK ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)
+#define EFI_AHCI_PORT_CMD_PMA BIT17
+#define EFI_AHCI_PORT_CMD_HPCP BIT18
+#define EFI_AHCI_PORT_CMD_MPSP BIT19
+#define EFI_AHCI_PORT_CMD_CPD BIT20
+#define EFI_AHCI_PORT_CMD_ESP BIT21
+#define EFI_AHCI_PORT_CMD_ATAPI BIT24
+#define EFI_AHCI_PORT_CMD_DLAE BIT25
+#define EFI_AHCI_PORT_CMD_ALPE BIT26
+#define EFI_AHCI_PORT_CMD_ASP BIT27
+#define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
+#define EFI_AHCI_PORT_CMD_ACTIVE (1 << 28 )
+#define EFI_AHCI_PORT_TFD 0x0020
+#define EFI_AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)
+#define EFI_AHCI_PORT_TFD_BSY BIT7
+#define EFI_AHCI_PORT_TFD_DRQ BIT3
+#define EFI_AHCI_PORT_TFD_ERR BIT0
+#define EFI_AHCI_PORT_TFD_ERR_MASK 0x00FF00
+#define EFI_AHCI_PORT_SIG 0x0024
+#define EFI_AHCI_PORT_SSTS 0x0028
+#define EFI_AHCI_PORT_SSTS_DET_MASK 0x000F
+#define EFI_AHCI_PORT_SSTS_DET 0x0001
+#define EFI_AHCI_PORT_SSTS_DET_PCE 0x0003
+#define EFI_AHCI_PORT_SSTS_SPD_MASK 0x00F0
+#define EFI_AHCI_PORT_SCTL 0x002C
+#define EFI_AHCI_PORT_SCTL_DET_MASK 0x000F
+#define EFI_AHCI_PORT_SCTL_MASK (~EFI_AHCI_PORT_SCTL_DET_MASK)
+#define EFI_AHCI_PORT_SCTL_DET_INIT 0x0001
+#define EFI_AHCI_PORT_SCTL_DET_PHYCOMM 0x0003
+#define EFI_AHCI_PORT_SCTL_SPD_MASK 0x00F0
+#define EFI_AHCI_PORT_SCTL_IPM_MASK 0x0F00
+#define EFI_AHCI_PORT_SCTL_IPM_INIT 0x0300
+#define EFI_AHCI_PORT_SCTL_IPM_PSD 0x0100
+#define EFI_AHCI_PORT_SCTL_IPM_SSD 0x0200
+#define EFI_AHCI_PORT_SERR 0x0030
+#define EFI_AHCI_PORT_SERR_RDIE BIT0
+#define EFI_AHCI_PORT_SERR_RCE BIT1
+#define EFI_AHCI_PORT_SERR_TDIE BIT8
+#define EFI_AHCI_PORT_SERR_PCDIE BIT9
+#define EFI_AHCI_PORT_SERR_PE BIT10
+#define EFI_AHCI_PORT_SERR_IE BIT11
+#define EFI_AHCI_PORT_SERR_PRC BIT16
+#define EFI_AHCI_PORT_SERR_PIE BIT17
+#define EFI_AHCI_PORT_SERR_CW BIT18
+#define EFI_AHCI_PORT_SERR_BDE BIT19
+#define EFI_AHCI_PORT_SERR_DE BIT20
+#define EFI_AHCI_PORT_SERR_CRCE BIT21
+#define EFI_AHCI_PORT_SERR_HE BIT22
+#define EFI_AHCI_PORT_SERR_LSE BIT23
+#define EFI_AHCI_PORT_SERR_TSTE BIT24
+#define EFI_AHCI_PORT_SERR_UFT BIT25
+#define EFI_AHCI_PORT_SERR_EX BIT26
+#define EFI_AHCI_PORT_ERR_CLEAR 0xFFFFFFFF
+#define EFI_AHCI_PORT_SACT 0x0034
+#define EFI_AHCI_PORT_CI 0x0038
+#define EFI_AHCI_PORT_SNTF 0x003C
+
+
+#pragma pack(1)
+//
+// Command List structure includes total 32 entries.
+// The entry data structure is listed at the following.
+//
+typedef struct {
+ UINT32 AhciCmdCfl:5; //Command FIS Length
+ UINT32 AhciCmdA:1; //ATAPI
+ UINT32 AhciCmdW:1; //Write
+ UINT32 AhciCmdP:1; //Prefetchable
+ UINT32 AhciCmdR:1; //Reset
+ UINT32 AhciCmdB:1; //BIST
+ UINT32 AhciCmdC:1; //Clear Busy upon R_OK
+ UINT32 AhciCmdRsvd:1;
+ UINT32 AhciCmdPmp:4; //Port Multiplier Port
+ UINT32 AhciCmdPrdtl:16; //Physical Region Descriptor Table Length
+ UINT32 AhciCmdPrdbc; //Physical Region Descriptor Byte Count
+ UINT32 AhciCmdCtba; //Command Table Descriptor Base Address
+ UINT32 AhciCmdCtbau; //Command Table Descriptor Base Address Upper 32-BITs
+ UINT32 AhciCmdRsvd1[4];
+} EFI_AHCI_COMMAND_LIST;
+
+//
+// This is a software constructed FIS.
+// For data transfer operations, this is the H2D Register FIS format as
+// specified in the Serial ATA Revision 2.6 specification.
+//
+typedef struct {
+ UINT8 AhciCFisType;
+ UINT8 AhciCFisPmNum:4;
+ UINT8 AhciCFisRsvd:1;
+ UINT8 AhciCFisRsvd1:1;
+ UINT8 AhciCFisRsvd2:1;
+ UINT8 AhciCFisCmdInd:1;
+ UINT8 AhciCFisCmd;
+ UINT8 AhciCFisFeature;
+ UINT8 AhciCFisSecNum;
+ UINT8 AhciCFisClyLow;
+ UINT8 AhciCFisClyHigh;
+ UINT8 AhciCFisDevHead;
+ UINT8 AhciCFisSecNumExp;
+ UINT8 AhciCFisClyLowExp;
+ UINT8 AhciCFisClyHighExp;
+ UINT8 AhciCFisFeatureExp;
+ UINT8 AhciCFisSecCount;
+ UINT8 AhciCFisSecCountExp;
+ UINT8 AhciCFisRsvd3;
+ UINT8 AhciCFisControl;
+ UINT8 AhciCFisRsvd4[4];
+ UINT8 AhciCFisRsvd5[44];
+} EFI_AHCI_COMMAND_FIS;
+
+//
+// ACMD: ATAPI command (12 or 16 bytes)
+//
+typedef struct {
+ UINT8 AtapiCmd[0x10];
+} EFI_AHCI_ATAPI_COMMAND;
+
+//
+// Physical Region Descriptor Table includes up to 65535 entries
+// The entry data structure is listed at the following.
+// the actual entry number comes from the PRDTL field in the command
+// list entry for this command slot.
+//
+typedef struct {
+ UINT32 AhciPrdtDba; //Data Base Address
+ UINT32 AhciPrdtDbau; //Data Base Address Upper 32-BITs
+ UINT32 AhciPrdtRsvd;
+ UINT32 AhciPrdtDbc:22; //Data Byte Count
+ UINT32 AhciPrdtRsvd1:9;
+ UINT32 AhciPrdtIoc:1; //Interrupt on Completion
+} EFI_AHCI_COMMAND_PRDT;
+
+//
+// Command table data strucute which is pointed to by the entry in the command list
+//
+typedef struct {
+ EFI_AHCI_COMMAND_FIS CommandFis; // A software constructed FIS.
+ EFI_AHCI_ATAPI_COMMAND AtapiCmd; // 12 or 16 bytes ATAPI cmd.
+ UINT8 Reserved[0x30];
+ EFI_AHCI_COMMAND_PRDT PrdtTable[65535]; // The scatter/gather list for data transfer
+} EFI_AHCI_COMMAND_TABLE;
+
+//
+// Received FIS structure
+//
+typedef struct {
+ UINT8 AhciDmaSetupFis[0x1C]; // Dma Setup Fis: offset 0x00
+ UINT8 AhciDmaSetupFisRsvd[0x04];
+ UINT8 AhciPioSetupFis[0x14]; // Pio Setup Fis: offset 0x20
+ UINT8 AhciPioSetupFisRsvd[0x0C];
+ UINT8 AhciD2HRegisterFis[0x14]; // D2H Register Fis: offset 0x40
+ UINT8 AhciD2HRegisterFisRsvd[0x04];
+ UINT64 AhciSetDeviceBitsFis; // Set Device Bits Fix: offset 0x58
+ UINT8 AhciUnknownFis[0x40]; // Unkonwn Fis: offset 0x60
+ UINT8 AhciUnknownFisRsvd[0x60];
+} EFI_AHCI_RECEIVED_FIS;
+
+#pragma pack()
+
+typedef struct {
+ EFI_AHCI_RECEIVED_FIS *AhciRFis;
+ EFI_AHCI_COMMAND_LIST *AhciCmdList;
+ EFI_AHCI_COMMAND_TABLE *AhciCommandTable;
+ UINT64 MaxCommandListSize;
+ UINT64 MaxCommandTableSize;
+ UINT64 MaxReceiveFisSize;
+ VOID *MapRFis;
+ VOID *MapCmdList;
+ VOID *MapCommandTable;
+ VOID *MapBaseAddress;
+} EFI_AHCI_REGISTERS;
+
+/**
+ This function is used to send out ATAPI commands conforms to the Packet Command
+ with PIO Protocol.
+
+ @param Base Base address.
+ @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
+ @param Port The number of port.
+ @param PortMultiplier The number of port multiplier.
+ @param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
+
+ @retval EFI_SUCCESS send out the ATAPI packet command successfully
+ and device sends data successfully.
+ @retval EFI_DEVICE_ERROR the device failed to send data.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciPacketCommandExecute (
+ IN VOID *Base,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet
+ );
+
+/**
+ Start command for give slot on specific port.
+
+ @param Base Base address.
+ @param Port The number of port.
+ @param CommandSlot The number of CommandSlot.
+ @param Timeout The timeout value of start, uses 100ns as a unit.
+
+ @retval EFI_DEVICE_ERROR The command start unsuccessfully.
+ @retval EFI_TIMEOUT The operation is time out.
+ @retval EFI_SUCCESS The command start successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciStartCommand (
+ IN VOID *Base,
+ IN UINT8 Port,
+ IN UINT8 CommandSlot,
+ IN UINT64 Timeout
+ );
+
+/**
+ Stop command running for giving port
+
+ @param Base Base address.
+ @param Port The number of port.
+ @param Timeout The timeout value of stop, uses 100ns as a unit.
+
+ @retval EFI_DEVICE_ERROR The command stop unsuccessfully.
+ @retval EFI_TIMEOUT The operation is time out.
+ @retval EFI_SUCCESS The command stop successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciStopCommand (
+ IN VOID *Base,
+ IN UINT8 Port,
+ IN UINT64 Timeout
+ );
+
+#endif
+
diff --git a/Platforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.c b/Platforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.c
new file mode 100755
index 0000000..01a49b9
--- /dev/null
+++ b/Platforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.c
@@ -0,0 +1,2134 @@
+/** @file
+ This file implements ATA_PASSTHRU_PROCTOCOL and EXT_SCSI_PASSTHRU_PROTOCOL interfaces
+ for managed ATA controllers.
+
+ Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "AtaAtapiPassThru.h"
+
+//
+// EFI_DRIVER_BINDING_PROTOCOL instance
+//
+EFI_DRIVER_BINDING_PROTOCOL gAtaAtapiPassThruDriverBinding = {
+ AtaAtapiPassThruSupported,
+ AtaAtapiPassThruStart,
+ AtaAtapiPassThruStop,
+ 0xa,
+ NULL,
+ NULL
+};
+
+ATA_ATAPI_PASS_THRU_INSTANCE gAtaAtapiPassThruInstanceTemplate = {
+ ATA_ATAPI_PASS_THRU_SIGNATURE,
+ 0, // Controller Handle
+ NULL, // IdeControllerInit Protocol
+ { // AtaPassThruMode
+ //
+ // According to UEFI2.3 spec Section 12.10, Drivers for non-RAID ATA controllers should set
+ // both EFI_ATA_PASS_THRU_ATTRIBUTES_PHYSICAL and EFI_ATA_PASS_THRU_ATTRIBUTES_LOGICAL
+ // bits.
+ // Note that the driver doesn't support AtaPassThru non blocking I/O.
+ //
+ EFI_ATA_PASS_THRU_ATTRIBUTES_PHYSICAL | EFI_ATA_PASS_THRU_ATTRIBUTES_LOGICAL | EFI_ATA_PASS_THRU_ATTRIBUTES_NONBLOCKIO,
+ //
+ // IoAlign
+ //
+ sizeof (UINTN)
+ },
+ { // AtaPassThru
+ NULL,
+ AtaPassThruPassThru,
+ AtaPassThruGetNextPort,
+ AtaPassThruGetNextDevice,
+ AtaPassThruBuildDevicePath,
+ AtaPassThruGetDevice,
+ AtaPassThruResetPort,
+ AtaPassThruResetDevice
+ },
+ { // ExtScsiPassThruMode
+ //
+ // AdapterId
+ //
+ 0,
+ //
+ // According to UEFI2.3 spec Section 14.7, Drivers for non-RAID SCSI controllers should set
+ // both EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL and EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_LOGICAL
+ // bits.
+ // Note that the driver doesn't support ExtScsiPassThru non blocking I/O.
+ //
+ EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL | EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_LOGICAL,
+ //
+ // IoAlign
+ //
+ sizeof (UINTN)
+ },
+ { // ExtScsiPassThru
+ NULL,
+ ExtScsiPassThruPassThru,
+ ExtScsiPassThruGetNextTargetLun,
+ ExtScsiPassThruBuildDevicePath,
+ ExtScsiPassThruGetTargetLun,
+ ExtScsiPassThruResetChannel,
+ ExtScsiPassThruResetTargetLun,
+ ExtScsiPassThruGetNextTarget
+ },
+ EfiAtaUnknownMode, // Work Mode
+ { // AhciRegisters
+ 0
+ },
+ NULL, // DevicePath
+ { // DeviceList
+ NULL,
+ NULL
+ },
+ 0, // PreviousPort
+ 0, // PreviousPortMultiplier
+ 0, // PreviousTargetId
+ 0, // PreviousLun
+ NULL, // Timer event
+ { // NonBlocking TaskList
+ NULL,
+ NULL
+ }
+};
+
+ATAPI_DEVICE_PATH mAtapiDevicePathTemplate = {
+ {
+ MESSAGING_DEVICE_PATH,
+ MSG_ATAPI_DP,
+ (UINT8) (sizeof (ATAPI_DEVICE_PATH)),
+ (UINT8) ((sizeof (ATAPI_DEVICE_PATH)) >> 8),
+ },
+ 0,
+ 0,
+ 0
+};
+
+SATA_DEVICE_PATH mSataDevicePathTemplate = {
+ {
+ MESSAGING_DEVICE_PATH,
+ MSG_SATA_DP,
+ (UINT8) (sizeof (SATA_DEVICE_PATH)),
+ (UINT8) ((sizeof (SATA_DEVICE_PATH)) >> 8),
+ },
+ 0,
+ 0,
+ 0
+};
+
+UINT8 mScsiId[TARGET_MAX_BYTES] = {
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF
+};
+
+/**
+ Sends an ATA command to an ATA device that is attached to the ATA controller. This function
+ supports both blocking I/O and non-blocking I/O. The blocking I/O functionality is required,
+ and the non-blocking I/O functionality is optional.
+
+ @param[in] Port The port number of the ATA device to send the command.
+ @param[in] PortMultiplierPort The port multiplier port number of the ATA device to send the command.
+ If there is no port multiplier, then specify 0.
+ @param[in, out] Packet A pointer to the ATA command to send to the ATA device specified by Port
+ and PortMultiplierPort.
+ @param[in] Instance Pointer to the ATA_ATAPI_PASS_THRU_INSTANCE.
+ @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
+ used by non-blocking mode.
+
+ @retval EFI_SUCCESS The ATA command was sent by the host. For
+ bi-directional commands, InTransferLength bytes
+ were transferred from InDataBuffer. For
+ write and bi-directional commands, OutTransferLength
+ bytes were transferred by OutDataBuffer.
+ @retval EFI_BAD_BUFFER_SIZE The ATA command was not executed. The number
+ of bytes that could be transferred is returned
+ in InTransferLength. For write and bi-directional
+ commands, OutTransferLength bytes were transferred
+ by OutDataBuffer.
+ @retval EFI_NOT_READY The ATA command could not be sent because
+ there are too many ATA commands already
+ queued. The caller may retry again later.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting
+ to send the ATA command.
+ @retval EFI_INVALID_PARAMETER Port, PortMultiplierPort, or the contents
+ of Acb are invalid. The ATA command was
+ not sent, so no additional status information
+ is available.
+
+**/
+EFI_STATUS
+EFIAPI
+AtaPassThruPassThruExecute (
+ IN UINT16 Port,
+ IN UINT16 PortMultiplierPort,
+ IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,
+ IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
+ IN ATA_NONBLOCK_TASK *Task OPTIONAL
+ )
+{
+ EFI_ATA_PASS_THRU_CMD_PROTOCOL Protocol;
+ EFI_ATA_HC_WORK_MODE Mode;
+ EFI_STATUS Status;
+
+ Protocol = Packet->Protocol;
+
+ Mode = Instance->Mode;
+ switch (Mode) {
+ case EfiAtaIdeMode:
+ Status = EFI_DEVICE_ERROR;
+ break;
+ case EfiAtaAhciMode :
+ switch (Protocol) {
+ case EFI_ATA_PASS_THRU_PROTOCOL_ATA_NON_DATA:
+ Status = AhciNonDataTransfer (
+ Instance->AhciRegisters.MapBaseAddress,
+ &Instance->AhciRegisters,
+ (UINT8)Port,
+ (UINT8)PortMultiplierPort,
+ NULL,
+ 0,
+ Packet->Acb,
+ Packet->Asb,
+ Packet->Timeout,
+ Task
+ );
+ break;
+ case EFI_ATA_PASS_THRU_PROTOCOL_PIO_DATA_IN:
+ Status = AhciPioTransfer (
+ Instance->AhciRegisters.MapBaseAddress,
+ &Instance->AhciRegisters,
+ (UINT8)Port,
+ (UINT8)PortMultiplierPort,
+ NULL,
+ 0,
+ TRUE,
+ Packet->Acb,
+ Packet->Asb,
+ Packet->InDataBuffer,
+ Packet->InTransferLength,
+ Packet->Timeout,
+ Task
+ );
+ break;
+ case EFI_ATA_PASS_THRU_PROTOCOL_PIO_DATA_OUT:
+ Status = AhciPioTransfer (
+ Instance->AhciRegisters.MapBaseAddress,
+ &Instance->AhciRegisters,
+ (UINT8)Port,
+ (UINT8)PortMultiplierPort,
+ NULL,
+ 0,
+ FALSE,
+ Packet->Acb,
+ Packet->Asb,
+ Packet->OutDataBuffer,
+ Packet->OutTransferLength,
+ Packet->Timeout,
+ Task
+ );
+ break;
+ case EFI_ATA_PASS_THRU_PROTOCOL_UDMA_DATA_IN:
+ Status = AhciDmaTransfer (
+ Instance,
+ &Instance->AhciRegisters,
+ (UINT8)Port,
+ (UINT8)PortMultiplierPort,
+ NULL,
+ 0,
+ TRUE,
+ Packet->Acb,
+ Packet->Asb,
+ Packet->InDataBuffer,
+ Packet->InTransferLength,
+ Packet->Timeout,
+ Task
+ );
+ break;
+ case EFI_ATA_PASS_THRU_PROTOCOL_UDMA_DATA_OUT:
+ Status = AhciDmaTransfer (
+ Instance,
+ &Instance->AhciRegisters,
+ (UINT8)Port,
+ (UINT8)PortMultiplierPort,
+ NULL,
+ 0,
+ FALSE,
+ Packet->Acb,
+ Packet->Asb,
+ Packet->OutDataBuffer,
+ Packet->OutTransferLength,
+ Packet->Timeout,
+ Task
+ );
+ break;
+ default :
+ return EFI_UNSUPPORTED;
+ }
+ break;
+
+ default:
+ Status = EFI_DEVICE_ERROR;
+ break;
+ }
+
+ return Status;
+}
+
+/**
+ Call back function when the timer event is signaled.
+
+ @param[in] Event The Event this notify function registered to.
+ @param[in] Context Pointer to the context data registered to the
+ Event.
+
+**/
+VOID
+EFIAPI
+AsyncNonBlockingTransferRoutine (
+ EFI_EVENT Event,
+ VOID* Context
+ )
+{
+ LIST_ENTRY *Entry;
+ LIST_ENTRY *EntryHeader;
+ ATA_NONBLOCK_TASK *Task;
+ EFI_STATUS Status;
+ ATA_ATAPI_PASS_THRU_INSTANCE *Instance;
+
+ Instance = (ATA_ATAPI_PASS_THRU_INSTANCE *) Context;
+ EntryHeader = &Instance->NonBlockingTaskList;
+ //
+ // Get the Taks from the Taks List and execute it, until there is
+ // no task in the list or the device is busy with task (EFI_NOT_READY).
+ //
+ while (TRUE) {
+ if (!IsListEmpty (EntryHeader)) {
+ Entry = GetFirstNode (EntryHeader);
+ Task = ATA_NON_BLOCK_TASK_FROM_ENTRY (Entry);
+ } else {
+ return;
+ }
+
+ Status = AtaPassThruPassThruExecute (
+ Task->Port,
+ Task->PortMultiplier,
+ Task->Packet,
+ Instance,
+ Task
+ );
+
+ //
+ // If the data transfer meet a error, remove all tasks in the list since these tasks are
+ // associated with one task from Ata Bus and signal the event with error status.
+ //
+ if ((Status != EFI_NOT_READY) && (Status != EFI_SUCCESS)) {
+ DestroyAsynTaskList (Instance, TRUE);
+ break;
+ }
+
+ //
+ // For Non blocking mode, the Status of EFI_NOT_READY means the operation
+ // is not finished yet. Otherwise the operation is successful.
+ //
+ if (Status == EFI_NOT_READY) {
+ break;
+ } else {
+ RemoveEntryList (&Task->Link);
+ gBS->SignalEvent (Task->Event);
+ FreePool (Task);
+ }
+ }
+}
+
+/**
+ The Entry Point of module.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeAtaAtapiPassThru (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Install driver model protocol(s).
+ //
+ Status = EfiLibInstallDriverBindingComponentName2 (
+ ImageHandle,
+ SystemTable,
+ &gAtaAtapiPassThruDriverBinding,
+ ImageHandle,
+ &gAtaAtapiPassThruComponentName,
+ &gAtaAtapiPassThruComponentName2
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ Tests to see if this driver supports a given controller. If a child device is provided,
+ it further tests to see if this driver supports creating a handle for the specified child device.
+
+ This function checks to see if the driver specified by This supports the device specified by
+ ControllerHandle. Drivers will typically use the device path attached to
+ ControllerHandle and/or the services from the bus I/O abstraction attached to
+ ControllerHandle to determine if the driver supports ControllerHandle. This function
+ may be called many times during platform initialization. In order to reduce boot times, the tests
+ performed by this function must be very small, and take as little time as possible to execute. This
+ function must not change the state of any hardware devices, and this function must be aware that the
+ device specified by ControllerHandle may already be managed by the same driver or a
+ different driver. This function must match its calls to AllocatePages() with FreePages(),
+ AllocatePool() with FreePool(), and OpenProtocol() with CloseProtocol().
+ Because ControllerHandle may have been previously started by the same driver, if a protocol is
+ already in the opened state, then it must not be closed with CloseProtocol(). This is required
+ to guarantee the state of ControllerHandle is not modified by this function.
+
+ @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+ @param[in] ControllerHandle The handle of the controller to test. This handle
+ must support a protocol interface that supplies
+ an I/O abstraction to the driver.
+ @param[in] RemainingDevicePath A pointer to the remaining portion of a device path. This
+ parameter is ignored by device drivers, and is optional for bus
+ drivers. For bus drivers, if this parameter is not NULL, then
+ the bus driver must determine if the bus controller specified
+ by ControllerHandle and the child controller specified
+ by RemainingDevicePath are both supported by this
+ bus driver.
+
+ @retval EFI_SUCCESS The device specified by ControllerHandle and
+ RemainingDevicePath is supported by the driver specified by This.
+ @retval EFI_ALREADY_STARTED The device specified by ControllerHandle and
+ RemainingDevicePath is already being managed by the driver
+ specified by This.
+ @retval EFI_ACCESS_DENIED The device specified by ControllerHandle and
+ RemainingDevicePath is already being managed by a different
+ driver or an application that requires exclusive access.
+ Currently not implemented.
+ @retval EFI_UNSUPPORTED The device specified by ControllerHandle and
+ RemainingDevicePath is not supported by the driver specified by This.
+**/
+EFI_STATUS
+EFIAPI
+AtaAtapiPassThruSupported (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ )
+{
+ EFI_STATUS Status;
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeControllerInit;
+
+ EFI_DEV_PATH_PTR Node;
+
+ //
+ // Check RemainingDevicePath validation
+ //
+ if (RemainingDevicePath != NULL) {
+ //
+ // Check if RemainingDevicePath is the End of Device Path Node,
+ // if yes, go on checking other conditions
+ //
+ if (!IsDevicePathEnd (RemainingDevicePath)) {
+ //
+ // If RemainingDevicePath isn't the End of Device Path Node,
+ // check its validation
+ //
+ Node.DevPath = RemainingDevicePath;
+ if (Node.DevPath->Type != HARDWARE_DEVICE_PATH ||
+ Node.DevPath->SubType != HW_VENDOR_DP ||
+ DevicePathNodeLength(Node.DevPath) != sizeof(VENDOR_DEVICE_PATH)) {
+ return EFI_UNSUPPORTED;
+ }
+ }
+ }
+
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiIdeControllerInitProtocolGuid,
+ (VOID **) &IdeControllerInit,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_BY_DRIVER
+ );
+
+ if (EFI_ERROR (Status)) {
+ //
+ // EFI_ALREADY_STARTED is also an error
+ //
+ return Status;
+ }
+
+ //
+ // Close the I/O Abstraction(s) used to perform the supported test
+ //
+ gBS->CloseProtocol (
+ Controller,
+ &gEfiIdeControllerInitProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Starts a device controller or a bus controller.
+
+ The Start() function is designed to be invoked from the EFI boot service ConnectController().
+ As a result, much of the error checking on the parameters to Start() has been moved into this
+ common boot service. It is legal to call Start() from other locations,
+ but the following calling restrictions must be followed, or the system behavior will not be deterministic.
+ 1. ControllerHandle must be a valid EFI_HANDLE.
+ 2. If RemainingDevicePath is not NULL, then it must be a pointer to a naturally aligned
+ EFI_DEVICE_PATH_PROTOCOL.
+ 3. Prior to calling Start(), the Supported() function for the driver specified by This must
+ have been called with the same calling parameters, and Supported() must have returned EFI_SUCCESS.
+
+ @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+ @param[in] ControllerHandle The handle of the controller to start. This handle
+ must support a protocol interface that supplies
+ an I/O abstraction to the driver.
+ @param[in] RemainingDevicePath A pointer to the remaining portion of a device path. This
+ parameter is ignored by device drivers, and is optional for bus
+ drivers. For a bus driver, if this parameter is NULL, then handles
+ for all the children of Controller are created by this driver.
+ If this parameter is not NULL and the first Device Path Node is
+ not the End of Device Path Node, then only the handle for the
+ child device specified by the first Device Path Node of
+ RemainingDevicePath is created by this driver.
+ If the first Device Path Node of RemainingDevicePath is
+ the End of Device Path Node, no child handle is created by this
+ driver.
+
+ @retval EFI_SUCCESS The device was started.
+ @retval EFI_DEVICE_ERROR The device could not be started due to a device error.Currently not implemented.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval Others The driver failded to start the device.
+
+**/
+EFI_STATUS
+EFIAPI
+AtaAtapiPassThruStart (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ )
+{
+ EFI_STATUS Status;
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeControllerInit;
+ ATA_ATAPI_PASS_THRU_INSTANCE *Instance;
+
+ EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+ Status = EFI_SUCCESS;
+ IdeControllerInit = NULL;
+ Instance = NULL;
+
+ DEBUG ((EFI_D_INFO, "==AtaAtapiPassThru Start== Controller = %x\n", Controller));
+
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiIdeControllerInitProtocolGuid,
+ (VOID **) &IdeControllerInit,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_BY_DRIVER
+ );
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Open Ide_Controller_Init Error, Status=%r\n", Status));
+ goto ErrorExit;
+ }
+
+ //
+ // Allocate a buffer to store the ATA_ATAPI_PASS_THRU_INSTANCE data structure
+ //
+ Instance = AllocateCopyPool (sizeof (ATA_ATAPI_PASS_THRU_INSTANCE), &gAtaAtapiPassThruInstanceTemplate);
+ if (Instance == NULL) {
+ goto ErrorExit;
+ }
+
+ Instance->ControllerHandle = Controller;
+ Instance->IdeControllerInit = IdeControllerInit;
+ Instance->AtaPassThru.Mode = &Instance->AtaPassThruMode;
+ Instance->ExtScsiPassThru.Mode = &Instance->ExtScsiPassThruMode;
+ InitializeListHead(&Instance->DeviceList);
+ InitializeListHead(&Instance->NonBlockingTaskList);
+
+ Instance->TimerEvent = NULL;
+
+ Status = gBS->CreateEvent (
+ EVT_TIMER | EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ AsyncNonBlockingTransferRoutine,
+ Instance,
+ &Instance->TimerEvent
+ );
+ if (EFI_ERROR (Status)) {
+ goto ErrorExit;
+ }
+
+ //
+ // Set 1ms timer.
+ //
+ Status = gBS->SetTimer (Instance->TimerEvent, TimerPeriodic, 10000);
+ if (EFI_ERROR (Status)) {
+ goto ErrorExit;
+ }
+
+ //
+ // Enumerate all inserted ATA devices.
+ //
+ Status = EnumerateAttachedDevice (Instance);
+ if (EFI_ERROR (Status)) {
+ goto ErrorExit;
+ }
+
+ Status = Instance->IdeControllerInit->BuildDevicePath (Instance->IdeControllerInit, &NewDevicePathNode);
+ if (EFI_ERROR (Status)) {
+ goto ErrorExit;
+ }
+
+ DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) AllocatePool (END_DEVICE_PATH_LENGTH);
+ if (DevicePath == NULL) {
+ goto ErrorExit;
+ }
+
+ SetDevicePathEndNode (DevicePath);
+ Instance->DevicePath = AppendDevicePathNode (DevicePath, NewDevicePathNode);
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Controller,
+ &gEfiAtaPassThruProtocolGuid, &(Instance->AtaPassThru),
+ &gEfiExtScsiPassThruProtocolGuid, &(Instance->ExtScsiPassThru),
+ &gEfiDevicePathProtocolGuid,Instance->DevicePath,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+
+ErrorExit:
+ if (IdeControllerInit != NULL) {
+ gBS->CloseProtocol (
+ Controller,
+ &gEfiIdeControllerInitProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
+ }
+
+ if ((Instance != NULL) && (Instance->TimerEvent != NULL)) {
+ gBS->CloseEvent (Instance->TimerEvent);
+ }
+
+ //
+ // Remove all inserted ATA devices.
+ //
+ DestroyDeviceInfoList(Instance);
+
+ if (Instance != NULL) {
+ FreePool (Instance);
+ }
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Stops a device controller or a bus controller.
+
+ The Stop() function is designed to be invoked from the EFI boot service DisconnectController().
+ As a result, much of the error checking on the parameters to Stop() has been moved
+ into this common boot service. It is legal to call Stop() from other locations,
+ but the following calling restrictions must be followed, or the system behavior will not be deterministic.
+ 1. ControllerHandle must be a valid EFI_HANDLE that was used on a previous call to this
+ same driver's Start() function.
+ 2. The first NumberOfChildren handles of ChildHandleBuffer must all be a valid
+ EFI_HANDLE. In addition, all of these handles must have been created in this driver's
+ Start() function, and the Start() function must have called OpenProtocol() on
+ ControllerHandle with an Attribute of EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER.
+
+ @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+ @param[in] ControllerHandle A handle to the device being stopped. The handle must
+ support a bus specific I/O protocol for the driver
+ to use to stop the device.
+ @param[in] NumberOfChildren The number of child device handles in ChildHandleBuffer.
+ @param[in] ChildHandleBuffer An array of child handles to be freed. May be NULL
+ if NumberOfChildren is 0.
+
+ @retval EFI_SUCCESS The device was stopped.
+ @retval EFI_DEVICE_ERROR The device could not be stopped due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+AtaAtapiPassThruStop (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
+ )
+{
+ EFI_STATUS Status;
+ ATA_ATAPI_PASS_THRU_INSTANCE *Instance;
+ EFI_ATA_PASS_THRU_PROTOCOL *AtaPassThru;
+ EFI_AHCI_REGISTERS *AhciRegisters;
+
+ DEBUG ((EFI_D_INFO, "==AtaAtapiPassThru Stop== Controller = %x\n", Controller));
+
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiAtaPassThruProtocolGuid,
+ (VOID **) &AtaPassThru,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL
+ );
+
+ if (EFI_ERROR (Status)) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ Instance = ATA_PASS_THRU_PRIVATE_DATA_FROM_THIS (AtaPassThru);
+
+ //
+ // Close Non-Blocking timer and free Task list.
+ //
+ if (Instance->TimerEvent != NULL) {
+ gBS->CloseEvent (Instance->TimerEvent);
+ Instance->TimerEvent = NULL;
+ }
+ DestroyAsynTaskList (Instance, FALSE);
+
+ gBS->UninstallMultipleProtocolInterfaces (
+ Controller,
+ &gEfiAtaPassThruProtocolGuid, &(Instance->AtaPassThru),
+ &gEfiExtScsiPassThruProtocolGuid, &(Instance->ExtScsiPassThru),
+ &gEfiDevicePathProtocolGuid,Instance->DevicePath,
+ NULL
+ );
+
+ //
+ // Close protocols opened by AtaAtapiPassThru controller driver
+ //
+ gBS->CloseProtocol (
+ Controller,
+ &gEfiIdeControllerInitProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
+
+ //
+ // Free allocated resource
+ //
+ DestroyDeviceInfoList(Instance);
+
+ //
+ // If the current working mode is AHCI mode, then pre-allocated resource
+ // for AHCI initialization should be released.
+ //
+ if (Instance->Mode == EfiAtaAhciMode) {
+ AhciRegisters = &Instance->AhciRegisters;
+ FreePool (AhciRegisters->AhciCommandTable);
+ FreePool (AhciRegisters->AhciCmdList);
+ FreePool (AhciRegisters->AhciRFis);
+ }
+
+ FreePool (Instance);
+
+ return Status;
+}
+
+/**
+ Traverse the attached ATA devices list to find out the device to access.
+
+ @param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.
+ @param[in] Port The port number of the ATA device to send the command.
+ @param[in] PortMultiplierPort The port multiplier port number of the ATA device to send the command.
+ If there is no port multiplier, then specify 0.
+ @param[in] DeviceType The device type of the ATA device.
+
+ @retval The pointer to the data structure of the device info to access.
+
+**/
+LIST_ENTRY *
+EFIAPI
+SearchDeviceInfoList (
+ IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
+ IN UINT16 Port,
+ IN UINT16 PortMultiplier,
+ IN EFI_ATA_DEVICE_TYPE DeviceType
+ )
+{
+ EFI_ATA_DEVICE_INFO *DeviceInfo;
+ LIST_ENTRY *Node;
+
+ Node = GetFirstNode (&Instance->DeviceList);
+ while (!IsNull (&Instance->DeviceList, Node)) {
+ DeviceInfo = ATA_ATAPI_DEVICE_INFO_FROM_THIS (Node);
+
+ if ((DeviceInfo->Type == DeviceType) &&
+ (Port == DeviceInfo->Port) &&
+ (PortMultiplier == DeviceInfo->PortMultiplier)) {
+ return Node;
+ }
+
+ Node = GetNextNode (&Instance->DeviceList, Node);
+ }
+
+ return NULL;
+}
+
+/**
+ Allocate device info data structure to contain device info.
+ And insert the data structure to the tail of device list for tracing.
+
+ @param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.
+ @param[in] Port The port number of the ATA device to send the command.
+ @param[in] PortMultiplierPort The port multiplier port number of the ATA device to send the command.
+ If there is no port multiplier, then specify 0.
+ @param[in] DeviceType The device type of the ATA device.
+ @param[in] IdentifyData The data buffer to store the output of the IDENTIFY cmd.
+
+ @retval EFI_SUCCESS Successfully insert the ata device to the tail of device list.
+ @retval EFI_OUT_OF_RESOURCES Can not allocate enough resource for use.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateNewDeviceInfo (
+ IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
+ IN UINT16 Port,
+ IN UINT16 PortMultiplier,
+ IN EFI_ATA_DEVICE_TYPE DeviceType,
+ IN EFI_IDENTIFY_DATA *IdentifyData
+ )
+{
+ EFI_ATA_DEVICE_INFO *DeviceInfo;
+
+ DeviceInfo = AllocateZeroPool (sizeof (EFI_ATA_DEVICE_INFO));
+
+ if (DeviceInfo == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ DeviceInfo->Signature = ATA_ATAPI_DEVICE_SIGNATURE;
+ DeviceInfo->Port = Port;
+ DeviceInfo->PortMultiplier = PortMultiplier;
+ DeviceInfo->Type = DeviceType;
+
+ if (IdentifyData != NULL) {
+ DeviceInfo->IdentifyData = AllocateCopyPool (sizeof (EFI_IDENTIFY_DATA), IdentifyData);
+ if (DeviceInfo->IdentifyData == NULL) {
+ FreePool (DeviceInfo);
+ return EFI_OUT_OF_RESOURCES;
+ }
+ }
+
+ InsertTailList (&Instance->DeviceList, &DeviceInfo->Link);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Destroy all attached ATA devices info.
+
+ @param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.
+
+**/
+VOID
+EFIAPI
+DestroyDeviceInfoList (
+ IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance
+ )
+{
+ EFI_ATA_DEVICE_INFO *DeviceInfo;
+ LIST_ENTRY *Node;
+
+ Node = GetFirstNode (&Instance->DeviceList);
+ while (!IsNull (&Instance->DeviceList, Node)) {
+ DeviceInfo = ATA_ATAPI_DEVICE_INFO_FROM_THIS (Node);
+
+ Node = GetNextNode (&Instance->DeviceList, Node);
+
+ RemoveEntryList (&DeviceInfo->Link);
+ if (DeviceInfo->IdentifyData != NULL) {
+ FreePool (DeviceInfo->IdentifyData);
+ }
+ FreePool (DeviceInfo);
+ }
+}
+
+/**
+ Destroy all pending non blocking tasks.
+
+ @param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.
+ @param[in] IsSigEvent Indicate whether signal the task event when remove the
+ task.
+
+**/
+VOID
+EFIAPI
+DestroyAsynTaskList (
+ IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
+ IN BOOLEAN IsSigEvent
+ )
+{
+ LIST_ENTRY *Entry;
+ LIST_ENTRY *DelEntry;
+ ATA_NONBLOCK_TASK *Task;
+ EFI_TPL OldTpl;
+
+ OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+ if (!IsListEmpty (&Instance->NonBlockingTaskList)) {
+ //
+ // Free the Subtask list.
+ //
+ for (Entry = (&Instance->NonBlockingTaskList)->ForwardLink;
+ Entry != (&Instance->NonBlockingTaskList);
+ ) {
+ DelEntry = Entry;
+ Entry = Entry->ForwardLink;
+ Task = ATA_NON_BLOCK_TASK_FROM_ENTRY (DelEntry);
+
+ RemoveEntryList (DelEntry);
+ if (IsSigEvent) {
+ Task->Packet->Asb->AtaStatus = 0x01;
+ gBS->SignalEvent (Task->Event);
+ }
+ FreePool (Task);
+ }
+ }
+ gBS->RestoreTPL (OldTpl);
+}
+
+/**
+ Enumerate all attached ATA devices at IDE mode or AHCI mode separately.
+
+ The function is designed to enumerate all attached ATA devices.
+
+ @param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.
+
+ @retval EFI_SUCCESS Successfully enumerate attached ATA devices.
+ @retval EFI_DEVICE_ERROR The device could not be stopped due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+EnumerateAttachedDevice (
+ IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+
+ //Support only AHCI mode
+
+ //
+ // The ATA controller is working at AHCI mode
+ //
+ Instance->Mode = EfiAtaAhciMode;
+
+ Status = AhciModeInitialization (Instance);
+
+ if (EFI_ERROR (Status)) {
+ Status = EFI_DEVICE_ERROR;
+ }
+
+ return Status;
+}
+
+/**
+ Sends an ATA command to an ATA device that is attached to the ATA controller. This function
+ supports both blocking I/O and non-blocking I/O. The blocking I/O functionality is required,
+ and the non-blocking I/O functionality is optional.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] Port The port number of the ATA device to send the command.
+ @param[in] PortMultiplierPort The port multiplier port number of the ATA device to send the command.
+ If there is no port multiplier, then specify 0.
+ @param[in, out] Packet A pointer to the ATA command to send to the ATA device specified by Port
+ and PortMultiplierPort.
+ @param[in] Event If non-blocking I/O is not supported then Event is ignored, and blocking
+ I/O is performed. If Event is NULL, then blocking I/O is performed. If
+ Event is not NULL and non blocking I/O is supported, then non-blocking
+ I/O is performed, and Event will be signaled when the ATA command completes.
+
+ @retval EFI_SUCCESS The ATA command was sent by the host. For bi-directional commands,
+ InTransferLength bytes were transferred from InDataBuffer. For write and
+ bi-directional commands, OutTransferLength bytes were transferred by OutDataBuffer.
+ @retval EFI_BAD_BUFFER_SIZE The ATA command was not executed. The number of bytes that could be transferred
+ is returned in InTransferLength. For write and bi-directional commands,
+ OutTransferLength bytes were transferred by OutDataBuffer.
+ @retval EFI_NOT_READY The ATA command could not be sent because there are too many ATA commands
+ already queued. The caller may retry again later.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the ATA command.
+ @retval EFI_INVALID_PARAMETER Port, PortMultiplierPort, or the contents of Acb are invalid. The ATA
+ command was not sent, so no additional status information is available.
+
+**/
+EFI_STATUS
+EFIAPI
+AtaPassThruPassThru (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port,
+ IN UINT16 PortMultiplierPort,
+ IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,
+ IN EFI_EVENT Event OPTIONAL
+ )
+{
+ ATA_ATAPI_PASS_THRU_INSTANCE *Instance;
+ LIST_ENTRY *Node;
+ EFI_ATA_DEVICE_INFO *DeviceInfo;
+ EFI_IDENTIFY_DATA *IdentifyData;
+ UINT64 Capacity;
+ UINT32 MaxSectorCount;
+ ATA_NONBLOCK_TASK *Task;
+ EFI_TPL OldTpl;
+
+ Instance = ATA_PASS_THRU_PRIVATE_DATA_FROM_THIS (This);
+
+ if ((This->Mode->IoAlign > 1) && !IS_ALIGNED(Packet->InDataBuffer, This->Mode->IoAlign)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((This->Mode->IoAlign > 1) && !IS_ALIGNED(Packet->OutDataBuffer, This->Mode->IoAlign)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((This->Mode->IoAlign > 1) && !IS_ALIGNED(Packet->Asb, This->Mode->IoAlign)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // convert the transfer length from sector count to byte.
+ //
+ if (((Packet->Length & EFI_ATA_PASS_THRU_LENGTH_BYTES) == 0) &&
+ (Packet->InTransferLength != 0)) {
+ Packet->InTransferLength = Packet->InTransferLength * 0x200;
+ }
+
+ //
+ // convert the transfer length from sector count to byte.
+ //
+ if (((Packet->Length & EFI_ATA_PASS_THRU_LENGTH_BYTES) == 0) &&
+ (Packet->OutTransferLength != 0)) {
+ Packet->OutTransferLength = Packet->OutTransferLength * 0x200;
+ }
+
+ Node = SearchDeviceInfoList (Instance, Port, PortMultiplierPort, EfiIdeHarddisk);
+
+ if (Node == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check whether this device needs 48-bit addressing (ATAPI-6 ata device).
+ // Per ATA-6 spec, word83: bit15 is zero and bit14 is one.
+ // If bit10 is one, it means the ata device support 48-bit addressing.
+ //
+ DeviceInfo = ATA_ATAPI_DEVICE_INFO_FROM_THIS (Node);
+ IdentifyData = DeviceInfo->IdentifyData;
+ MaxSectorCount = 0x100;
+ if ((IdentifyData->AtaData.command_set_supported_83 & (BIT10 | BIT15 | BIT14)) == 0x4400) {
+ Capacity = *((UINT64 *)IdentifyData->AtaData.maximum_lba_for_48bit_addressing);
+ if (Capacity > 0xFFFFFFF) {
+ //
+ // Capacity exceeds 120GB. 48-bit addressing is really needed
+ // In this case, the max sector count is 0x10000
+ //
+ MaxSectorCount = 0x10000;
+ }
+ }
+
+ //
+ // If the data buffer described by InDataBuffer/OutDataBuffer and InTransferLength/OutTransferLength
+ // is too big to be transferred in a single command, then no data is transferred and EFI_BAD_BUFFER_SIZE
+ // is returned.
+ //
+ if (((Packet->InTransferLength != 0) && (Packet->InTransferLength > MaxSectorCount * 0x200)) ||
+ ((Packet->OutTransferLength != 0) && (Packet->OutTransferLength > MaxSectorCount * 0x200))) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ //
+ // For non-blocking mode, queue the Task into the list.
+ //
+ if (Event != NULL) {
+ Task = AllocateZeroPool (sizeof (ATA_NONBLOCK_TASK));
+ if (Task == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Task->Signature = ATA_NONBLOCKING_TASK_SIGNATURE;
+ Task->Port = Port;
+ Task->PortMultiplier = PortMultiplierPort;
+ Task->Packet = Packet;
+ Task->Event = Event;
+ Task->IsStart = FALSE;
+ Task->RetryTimes = 0;
+
+ OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+ InsertTailList (&Instance->NonBlockingTaskList, &Task->Link);
+ gBS->RestoreTPL (OldTpl);
+
+ return EFI_SUCCESS;
+ } else {
+ return AtaPassThruPassThruExecute (
+ Port,
+ PortMultiplierPort,
+ Packet,
+ Instance,
+ NULL
+ );
+ }
+}
+
+/**
+ Used to retrieve the list of legal port numbers for ATA devices on an ATA controller.
+ These can either be the list of ports where ATA devices are actually present or the
+ list of legal port numbers for the ATA controller. Regardless, the caller of this
+ function must probe the port number returned to see if an ATA device is actually
+ present at that location on the ATA controller.
+
+ The GetNextPort() function retrieves the port number on an ATA controller. If on input
+ Port is 0xFFFF, then the port number of the first port on the ATA controller is returned
+ in Port and EFI_SUCCESS is returned.
+
+ If Port is a port number that was returned on a previous call to GetNextPort(), then the
+ port number of the next port on the ATA controller is returned in Port, and EFI_SUCCESS
+ is returned. If Port is not 0xFFFF and Port was not returned on a previous call to
+ GetNextPort(), then EFI_INVALID_PARAMETER is returned.
+
+ If Port is the port number of the last port on the ATA controller, then EFI_NOT_FOUND is
+ returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in, out] Port On input, a pointer to the port number on the ATA controller.
+ On output, a pointer to the next port number on the ATA
+ controller. An input value of 0xFFFF retrieves the first port
+ number on the ATA controller.
+
+ @retval EFI_SUCCESS The next port number on the ATA controller was returned in Port.
+ @retval EFI_NOT_FOUND There are no more ports on this ATA controller.
+ @retval EFI_INVALID_PARAMETER Port is not 0xFFFF and Port was not returned on a previous call
+ to GetNextPort().
+
+**/
+EFI_STATUS
+EFIAPI
+AtaPassThruGetNextPort (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN OUT UINT16 *Port
+ )
+{
+ ATA_ATAPI_PASS_THRU_INSTANCE *Instance;
+ LIST_ENTRY *Node;
+ EFI_ATA_DEVICE_INFO *DeviceInfo;
+
+ Instance = ATA_PASS_THRU_PRIVATE_DATA_FROM_THIS (This);
+
+ if (Port == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (*Port == 0xFFFF) {
+ //
+ // If the Port is all 0xFF's, start to traverse the device list from the beginning
+ //
+ Node = GetFirstNode (&Instance->DeviceList);
+
+ while (!IsNull (&Instance->DeviceList, Node)) {
+ DeviceInfo = ATA_ATAPI_DEVICE_INFO_FROM_THIS (Node);
+
+ if (DeviceInfo->Type == EfiIdeHarddisk) {
+ *Port = DeviceInfo->Port;
+ goto Exit;
+ }
+
+ Node = GetNextNode (&Instance->DeviceList, Node);
+ }
+
+ return EFI_NOT_FOUND;
+ } else if (*Port == Instance->PreviousPort) {
+ Node = GetFirstNode (&Instance->DeviceList);
+
+ while (!IsNull (&Instance->DeviceList, Node)) {
+ DeviceInfo = ATA_ATAPI_DEVICE_INFO_FROM_THIS (Node);
+
+ if ((DeviceInfo->Type == EfiIdeHarddisk) &&
+ (DeviceInfo->Port > *Port)){
+ *Port = DeviceInfo->Port;
+ goto Exit;
+ }
+
+ Node = GetNextNode (&Instance->DeviceList, Node);
+ }
+
+ return EFI_NOT_FOUND;
+ } else {
+ //
+ // Port is not equal to 0xFFFF and also not equal to previous return value
+ //
+ return EFI_INVALID_PARAMETER;
+ }
+
+Exit:
+ //
+ // Update the PreviousPort and PreviousPortMultiplier.
+ //
+ Instance->PreviousPort = *Port;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Used to retrieve the list of legal port multiplier port numbers for ATA devices on a port of an ATA
+ controller. These can either be the list of port multiplier ports where ATA devices are actually
+ present on port or the list of legal port multiplier ports on that port. Regardless, the caller of this
+ function must probe the port number and port multiplier port number returned to see if an ATA
+ device is actually present.
+
+ The GetNextDevice() function retrieves the port multiplier port number of an ATA device
+ present on a port of an ATA controller.
+
+ If PortMultiplierPort points to a port multiplier port number value that was returned on a
+ previous call to GetNextDevice(), then the port multiplier port number of the next ATA device
+ on the port of the ATA controller is returned in PortMultiplierPort, and EFI_SUCCESS is
+ returned.
+
+ If PortMultiplierPort points to 0xFFFF, then the port multiplier port number of the first
+ ATA device on port of the ATA controller is returned in PortMultiplierPort and
+ EFI_SUCCESS is returned.
+
+ If PortMultiplierPort is not 0xFFFF and the value pointed to by PortMultiplierPort
+ was not returned on a previous call to GetNextDevice(), then EFI_INVALID_PARAMETER
+ is returned.
+
+ If PortMultiplierPort is the port multiplier port number of the last ATA device on the port of
+ the ATA controller, then EFI_NOT_FOUND is returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] Port The port number present on the ATA controller.
+ @param[in, out] PortMultiplierPort On input, a pointer to the port multiplier port number of an
+ ATA device present on the ATA controller.
+ If on input a PortMultiplierPort of 0xFFFF is specified,
+ then the port multiplier port number of the first ATA device
+ is returned. On output, a pointer to the port multiplier port
+ number of the next ATA device present on an ATA controller.
+
+ @retval EFI_SUCCESS The port multiplier port number of the next ATA device on the port
+ of the ATA controller was returned in PortMultiplierPort.
+ @retval EFI_NOT_FOUND There are no more ATA devices on this port of the ATA controller.
+ @retval EFI_INVALID_PARAMETER PortMultiplierPort is not 0xFFFF, and PortMultiplierPort was not
+ returned on a previous call to GetNextDevice().
+
+**/
+EFI_STATUS
+EFIAPI
+AtaPassThruGetNextDevice (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port,
+ IN OUT UINT16 *PortMultiplierPort
+ )
+{
+ ATA_ATAPI_PASS_THRU_INSTANCE *Instance;
+ LIST_ENTRY *Node;
+ EFI_ATA_DEVICE_INFO *DeviceInfo;
+
+ Instance = ATA_PASS_THRU_PRIVATE_DATA_FROM_THIS (This);
+
+ if (PortMultiplierPort == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (*PortMultiplierPort == 0xFFFF) {
+ //
+ // If the PortMultiplierPort is all 0xFF's, start to traverse the device list from the beginning
+ //
+ Node = GetFirstNode (&Instance->DeviceList);
+
+ while (!IsNull (&Instance->DeviceList, Node)) {
+ DeviceInfo = ATA_ATAPI_DEVICE_INFO_FROM_THIS (Node);
+
+ if ((DeviceInfo->Type == EfiIdeHarddisk) &&
+ (DeviceInfo->Port == Port)){
+ *PortMultiplierPort = DeviceInfo->PortMultiplier;
+ goto Exit;
+ }
+
+ Node = GetNextNode (&Instance->DeviceList, Node);
+ }
+
+ return EFI_NOT_FOUND;
+ } else if (*PortMultiplierPort == Instance->PreviousPortMultiplier) {
+ Node = GetFirstNode (&Instance->DeviceList);
+
+ while (!IsNull (&Instance->DeviceList, Node)) {
+ DeviceInfo = ATA_ATAPI_DEVICE_INFO_FROM_THIS (Node);
+
+ if ((DeviceInfo->Type == EfiIdeHarddisk) &&
+ (DeviceInfo->Port == Port) &&
+ (DeviceInfo->PortMultiplier > *PortMultiplierPort)){
+ *PortMultiplierPort = DeviceInfo->PortMultiplier;
+ goto Exit;
+ }
+
+ Node = GetNextNode (&Instance->DeviceList, Node);
+ }
+
+ return EFI_NOT_FOUND;
+ } else {
+ //
+ // PortMultiplierPort is not equal to 0xFFFF and also not equal to previous return value
+ //
+ return EFI_INVALID_PARAMETER;
+ }
+
+Exit:
+ //
+ // Update the PreviousPort and PreviousPortMultiplier.
+ //
+ Instance->PreviousPortMultiplier = *PortMultiplierPort;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Used to allocate and build a device path node for an ATA device on an ATA controller.
+
+ The BuildDevicePath() function allocates and builds a single device node for the ATA
+ device specified by Port and PortMultiplierPort. If the ATA device specified by Port and
+ PortMultiplierPort is not present on the ATA controller, then EFI_NOT_FOUND is returned.
+ If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned. If there are not enough
+ resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.
+
+ Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of
+ DevicePath are initialized to describe the ATA device specified by Port and PortMultiplierPort,
+ and EFI_SUCCESS is returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] Port Port specifies the port number of the ATA device for which a
+ device path node is to be allocated and built.
+ @param[in] PortMultiplierPort The port multiplier port number of the ATA device for which a
+ device path node is to be allocated and built. If there is no
+ port multiplier, then specify 0.
+ @param[in, out] DevicePath A pointer to a single device path node that describes the ATA
+ device specified by Port and PortMultiplierPort. This function
+ is responsible for allocating the buffer DevicePath with the
+ boot service AllocatePool(). It is the caller's responsibility
+ to free DevicePath when the caller is finished with DevicePath.
+ @retval EFI_SUCCESS The device path node that describes the ATA device specified by
+ Port and PortMultiplierPort was allocated and returned in DevicePath.
+ @retval EFI_NOT_FOUND The ATA device specified by Port and PortMultiplierPort does not
+ exist on the ATA controller.
+ @retval EFI_INVALID_PARAMETER DevicePath is NULL.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate DevicePath.
+
+**/
+EFI_STATUS
+EFIAPI
+AtaPassThruBuildDevicePath (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port,
+ IN UINT16 PortMultiplierPort,
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
+ )
+{
+ EFI_DEV_PATH *DevicePathNode;
+ ATA_ATAPI_PASS_THRU_INSTANCE *Instance;
+ LIST_ENTRY *Node;
+
+ Instance = ATA_PASS_THRU_PRIVATE_DATA_FROM_THIS (This);
+
+ //
+ // Validate parameters passed in.
+ //
+ if (DevicePath == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Node = SearchDeviceInfoList(Instance, Port, PortMultiplierPort, EfiIdeHarddisk);
+ if (Node == NULL) {
+ return EFI_NOT_FOUND;
+ }
+
+ DevicePathNode = AllocateCopyPool (sizeof (SATA_DEVICE_PATH), &mSataDevicePathTemplate);
+ if (DevicePathNode == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ DevicePathNode->Sata.HBAPortNumber = Port;
+ DevicePathNode->Sata.PortMultiplierPortNumber = PortMultiplierPort;
+ DevicePathNode->Sata.Lun = 0;
+
+ *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) DevicePathNode;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Used to translate a device path node to a port number and port multiplier port number.
+
+ The GetDevice() function determines the port and port multiplier port number associated with
+ the ATA device described by DevicePath. If DevicePath is a device path node type that the
+ ATA Pass Thru driver supports, then the ATA Pass Thru driver will attempt to translate the contents
+ DevicePath into a port number and port multiplier port number.
+
+ If this translation is successful, then that port number and port multiplier port number are returned
+ in Port and PortMultiplierPort, and EFI_SUCCESS is returned.
+
+ If DevicePath, Port, or PortMultiplierPort are NULL, then EFI_INVALID_PARAMETER is returned.
+
+ If DevicePath is not a device path node type that the ATA Pass Thru driver supports, then
+ EFI_UNSUPPORTED is returned.
+
+ If DevicePath is a device path node type that the ATA Pass Thru driver supports, but there is not
+ a valid translation from DevicePath to a port number and port multiplier port number, then
+ EFI_NOT_FOUND is returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] DevicePath A pointer to the device path node that describes an ATA device on the
+ ATA controller.
+ @param[out] Port On return, points to the port number of an ATA device on the ATA controller.
+ @param[out] PortMultiplierPort On return, points to the port multiplier port number of an ATA device
+ on the ATA controller.
+
+ @retval EFI_SUCCESS DevicePath was successfully translated to a port number and port multiplier
+ port number, and they were returned in Port and PortMultiplierPort.
+ @retval EFI_INVALID_PARAMETER DevicePath is NULL.
+ @retval EFI_INVALID_PARAMETER Port is NULL.
+ @retval EFI_INVALID_PARAMETER PortMultiplierPort is NULL.
+ @retval EFI_UNSUPPORTED This driver does not support the device path node type in DevicePath.
+ @retval EFI_NOT_FOUND A valid translation from DevicePath to a port number and port multiplier
+ port number does not exist.
+**/
+EFI_STATUS
+EFIAPI
+AtaPassThruGetDevice (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ OUT UINT16 *Port,
+ OUT UINT16 *PortMultiplierPort
+ )
+{
+ EFI_DEV_PATH *DevicePathNode;
+ ATA_ATAPI_PASS_THRU_INSTANCE *Instance;
+ LIST_ENTRY *Node;
+
+ Instance = ATA_PASS_THRU_PRIVATE_DATA_FROM_THIS (This);
+
+ //
+ // Validate parameters passed in.
+ //
+ if (DevicePath == NULL || Port == NULL || PortMultiplierPort == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check whether the DevicePath belongs to SCSI_DEVICE_PATH or ATAPI_DEVICE_PATH
+ //
+ if ((DevicePath->Type != MESSAGING_DEVICE_PATH) ||
+ ((DevicePath->SubType != MSG_SATA_DP) &&
+ (DevicePath->SubType != MSG_ATAPI_DP)) ||
+ ((DevicePathNodeLength(DevicePath) != sizeof(ATAPI_DEVICE_PATH)) &&
+ (DevicePathNodeLength(DevicePath) != sizeof(SATA_DEVICE_PATH)))) {
+ return EFI_UNSUPPORTED;
+ }
+
+ DevicePathNode = (EFI_DEV_PATH *) DevicePath;
+
+ *Port = DevicePathNode->Sata.HBAPortNumber;
+ *PortMultiplierPort = DevicePathNode->Sata.PortMultiplierPortNumber;
+
+ Node = SearchDeviceInfoList(Instance, *Port, *PortMultiplierPort, EfiIdeHarddisk);
+
+ if (Node == NULL) {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Resets a specific port on the ATA controller. This operation also resets all the ATA devices
+ connected to the port.
+
+ The ResetChannel() function resets an a specific port on an ATA controller. This operation
+ resets all the ATA devices connected to that port. If this ATA controller does not support
+ a reset port operation, then EFI_UNSUPPORTED is returned.
+
+ If a device error occurs while executing that port reset operation, then EFI_DEVICE_ERROR is
+ returned.
+
+ If a timeout occurs during the execution of the port reset operation, then EFI_TIMEOUT is returned.
+
+ If the port reset operation is completed, then EFI_SUCCESS is returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] Port The port number on the ATA controller.
+
+ @retval EFI_SUCCESS The ATA controller port was reset.
+ @retval EFI_UNSUPPORTED The ATA controller does not support a port reset operation.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to reset the ATA port.
+ @retval EFI_TIMEOUT A timeout occurred while attempting to reset the ATA port.
+
+**/
+EFI_STATUS
+EFIAPI
+AtaPassThruResetPort (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Resets an ATA device that is connected to an ATA controller.
+
+ The ResetDevice() function resets the ATA device specified by Port and PortMultiplierPort.
+ If this ATA controller does not support a device reset operation, then EFI_UNSUPPORTED is
+ returned.
+
+ If Port or PortMultiplierPort are not in a valid range for this ATA controller, then
+ EFI_INVALID_PARAMETER is returned.
+
+ If a device error occurs while executing that device reset operation, then EFI_DEVICE_ERROR
+ is returned.
+
+ If a timeout occurs during the execution of the device reset operation, then EFI_TIMEOUT is
+ returned.
+
+ If the device reset operation is completed, then EFI_SUCCESS is returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] Port Port represents the port number of the ATA device to be reset.
+ @param[in] PortMultiplierPort The port multiplier port number of the ATA device to reset.
+ If there is no port multiplier, then specify 0.
+ @retval EFI_SUCCESS The ATA device specified by Port and PortMultiplierPort was reset.
+ @retval EFI_UNSUPPORTED The ATA controller does not support a device reset operation.
+ @retval EFI_INVALID_PARAMETER Port or PortMultiplierPort are invalid.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to reset the ATA device
+ specified by Port and PortMultiplierPort.
+ @retval EFI_TIMEOUT A timeout occurred while attempting to reset the ATA device
+ specified by Port and PortMultiplierPort.
+
+**/
+EFI_STATUS
+EFIAPI
+AtaPassThruResetDevice (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port,
+ IN UINT16 PortMultiplierPort
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Sends a SCSI Request Packet to a SCSI device that is attached to the SCSI channel. This function
+ supports both blocking I/O and nonblocking I/O. The blocking I/O functionality is required, and the
+ nonblocking I/O functionality is optional.
+
+ @param This A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance.
+ @param Target The Target is an array of size TARGET_MAX_BYTES and it represents
+ the id of the SCSI device to send the SCSI Request Packet. Each
+ transport driver may choose to utilize a subset of this size to suit the needs
+ of transport target representation. For example, a Fibre Channel driver
+ may use only 8 bytes (WWN) to represent an FC target.
+ @param Lun The LUN of the SCSI device to send the SCSI Request Packet.
+ @param Packet A pointer to the SCSI Request Packet to send to the SCSI device
+ specified by Target and Lun.
+ @param Event If nonblocking I/O is not supported then Event is ignored, and blocking
+ I/O is performed. If Event is NULL, then blocking I/O is performed. If
+ Event is not NULL and non blocking I/O is supported, then
+ nonblocking I/O is performed, and Event will be signaled when the
+ SCSI Request Packet completes.
+
+ @retval EFI_SUCCESS The SCSI Request Packet was sent by the host. For bi-directional
+ commands, InTransferLength bytes were transferred from
+ InDataBuffer. For write and bi-directional commands,
+ OutTransferLength bytes were transferred by
+ OutDataBuffer.
+ @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was not executed. The number of bytes that
+ could be transferred is returned in InTransferLength. For write
+ and bi-directional commands, OutTransferLength bytes were
+ transferred by OutDataBuffer.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there are too many
+ SCSI Request Packets already queued. The caller may retry again later.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the SCSI Request
+ Packet.
+ @retval EFI_INVALID_PARAMETER Target, Lun, or the contents of ScsiRequestPacket are invalid.
+ @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not supported
+ by the host adapter. This includes the case of Bi-directional SCSI
+ commands not supported by the implementation. The SCSI Request
+ Packet was not sent, so no additional status information is available.
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute.
+
+**/
+EFI_STATUS
+EFIAPI
+ExtScsiPassThruPassThru (
+ IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This,
+ IN UINT8 *Target,
+ IN UINT64 Lun,
+ IN OUT EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet,
+ IN EFI_EVENT Event OPTIONAL
+ )
+{
+ EFI_STATUS Status;
+ ATA_ATAPI_PASS_THRU_INSTANCE *Instance;
+ UINT8 Port;
+ UINT8 PortMultiplier;
+ EFI_ATA_HC_WORK_MODE Mode;
+ LIST_ENTRY *Node;
+ EFI_ATA_DEVICE_INFO *DeviceInfo;
+
+ Instance = EXT_SCSI_PASS_THRU_PRIVATE_DATA_FROM_THIS (This);
+
+ if ((Packet == NULL) || (Packet->Cdb == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Don't support variable length CDB
+ //
+ if ((Packet->CdbLength != 6) && (Packet->CdbLength != 10) &&
+ (Packet->CdbLength != 12) && (Packet->CdbLength != 16)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((This->Mode->IoAlign > 1) && !IS_ALIGNED(Packet->InDataBuffer, This->Mode->IoAlign)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((This->Mode->IoAlign > 1) && !IS_ALIGNED(Packet->OutDataBuffer, This->Mode->IoAlign)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((This->Mode->IoAlign > 1) && !IS_ALIGNED(Packet->SenseData, This->Mode->IoAlign)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // For ATAPI device, doesn't support multiple LUN device.
+ //
+ if (Lun != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // The layout of Target array:
+ // ________________________________________________________________________
+ // | Byte 0 | Byte 1 | ... | TARGET_MAX_BYTES - 1 |
+ // |_____________________|_____________________|_____|______________________|
+ // | | The port multiplier | | |
+ // | The port number | port number | N/A | N/A |
+ // |_____________________|_____________________|_____|______________________|
+ //
+ // For ATAPI device, 2 bytes is enough to represent the location of SCSI device.
+ //
+ Port = Target[0];
+ PortMultiplier = Target[1];
+
+ Node = SearchDeviceInfoList(Instance, Port, PortMultiplier, EfiIdeCdrom);
+ if (Node == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ DeviceInfo = ATA_ATAPI_DEVICE_INFO_FROM_THIS (Node);
+
+ //
+ // ATA_CMD_IDENTIFY_DEVICE cmd is a ATA cmd but not a SCSI cmd.
+ // Normally it should NOT be passed down through ExtScsiPassThru protocol interface.
+ // But to response EFI_DISK_INFO.Identify() request from ScsiDisk, we should handle this command.
+ //
+ if (*((UINT8*)Packet->Cdb) == ATA_CMD_IDENTIFY_DEVICE) {
+ CopyMem (Packet->InDataBuffer, DeviceInfo->IdentifyData, sizeof (EFI_IDENTIFY_DATA));
+ return EFI_SUCCESS;
+ }
+
+ Mode = Instance->Mode;
+ switch (Mode) {
+ case EfiAtaAhciMode:
+ Status = AhciPacketCommandExecute (Instance->AhciRegisters.MapBaseAddress, &Instance->AhciRegisters, Port, PortMultiplier, Packet);
+ break;
+ default :
+ Status = EFI_DEVICE_ERROR;
+ break;
+ }
+
+ return Status;
+}
+
+/**
+ Used to retrieve the list of legal Target IDs and LUNs for SCSI devices on a SCSI channel. These
+ can either be the list SCSI devices that are actually present on the SCSI channel, or the list of legal
+ Target Ids and LUNs for the SCSI channel. Regardless, the caller of this function must probe the
+ Target ID and LUN returned to see if a SCSI device is actually present at that location on the SCSI
+ channel.
+
+ @param This A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance.
+ @param Target On input, a pointer to the Target ID (an array of size
+ TARGET_MAX_BYTES) of a SCSI device present on the SCSI channel.
+ On output, a pointer to the Target ID (an array of
+ TARGET_MAX_BYTES) of the next SCSI device present on a SCSI
+ channel. An input value of 0xF(all bytes in the array are 0xF) in the
+ Target array retrieves the Target ID of the first SCSI device present on a
+ SCSI channel.
+ @param Lun On input, a pointer to the LUN of a SCSI device present on the SCSI
+ channel. On output, a pointer to the LUN of the next SCSI device present
+ on a SCSI channel.
+
+ @retval EFI_SUCCESS The Target ID and LUN of the next SCSI device on the SCSI
+ channel was returned in Target and Lun.
+ @retval EFI_INVALID_PARAMETER Target array is not all 0xF, and Target and Lun were
+ not returned on a previous call to GetNextTargetLun().
+ @retval EFI_NOT_FOUND There are no more SCSI devices on this SCSI channel.
+
+**/
+EFI_STATUS
+EFIAPI
+ExtScsiPassThruGetNextTargetLun (
+ IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This,
+ IN OUT UINT8 **Target,
+ IN OUT UINT64 *Lun
+ )
+{
+ ATA_ATAPI_PASS_THRU_INSTANCE *Instance;
+ LIST_ENTRY *Node;
+ EFI_ATA_DEVICE_INFO *DeviceInfo;
+ UINT8 *Target8;
+ UINT16 *Target16;
+
+ Instance = EXT_SCSI_PASS_THRU_PRIVATE_DATA_FROM_THIS (This);
+
+ if (Target == NULL || Lun == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (*Target == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Target8 = *Target;
+ Target16 = (UINT16 *)*Target;
+
+ if (CompareMem(Target8, mScsiId, TARGET_MAX_BYTES) != 0) {
+ //
+ // For ATAPI device, we use 2 least significant bytes to represent the location of SCSI device.
+ // So the higher bytes in Target array should be 0xFF.
+ //
+ if (CompareMem (&Target8[2], &mScsiId[2], TARGET_MAX_BYTES - 2) != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // When Target is not all 0xFF's, compare 2 least significant bytes with
+ // previous target id to see if it is returned by previous call.
+ //
+ if ((*Target16 != Instance->PreviousTargetId) ||
+ (*Lun != Instance->PreviousLun)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Traverse the whole device list to find the next cdrom closed to
+ // the device signified by Target[0] and Target[1].
+ //
+ // Note that we here use a tricky way to find the next cdrom :
+ // All ata devices are detected and inserted into the device list
+ // sequentially.
+ //
+ Node = GetFirstNode (&Instance->DeviceList);
+
+ while (!IsNull (&Instance->DeviceList, Node)) {
+ DeviceInfo = ATA_ATAPI_DEVICE_INFO_FROM_THIS (Node);
+
+ if ((DeviceInfo->Type == EfiIdeCdrom) &&
+ ((Target8[0] < DeviceInfo->Port) ||
+ ((Target8[0] == DeviceInfo->Port) &&
+ (Target8[1] < DeviceInfo->PortMultiplier)))) {
+ Target8[0] = (UINT8)DeviceInfo->Port;
+ Target8[1] = (UINT8)DeviceInfo->PortMultiplier;
+ goto Exit;
+ }
+
+ Node = GetNextNode (&Instance->DeviceList, Node);
+ }
+
+ return EFI_NOT_FOUND;
+ } else {
+ //
+ // If the array is all 0xFF's, start to traverse the device list from the beginning
+ //
+ Node = GetFirstNode (&Instance->DeviceList);
+ while (!IsNull (&Instance->DeviceList, Node)) {
+ DeviceInfo = ATA_ATAPI_DEVICE_INFO_FROM_THIS (Node);
+
+ if (DeviceInfo->Type == EfiIdeCdrom) {
+ Target8[0] = (UINT8)DeviceInfo->Port;
+ Target8[1] = (UINT8)DeviceInfo->PortMultiplier;
+ goto Exit;
+ }
+
+ Node = GetNextNode (&Instance->DeviceList, Node);
+ }
+
+ return EFI_NOT_FOUND;
+ }
+
+Exit:
+ *Lun = 0;
+
+ //
+ // Update the PreviousTargetId.
+ //
+ Instance->PreviousTargetId = *Target16;
+ Instance->PreviousLun = *Lun;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Used to allocate and build a device path node for a SCSI device on a SCSI channel.
+
+ @param This A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance.
+ @param Target The Target is an array of size TARGET_MAX_BYTES and it specifies the
+ Target ID of the SCSI device for which a device path node is to be
+ allocated and built. Transport drivers may chose to utilize a subset of
+ this size to suit the representation of targets. For example, a Fibre
+ Channel driver may use only 8 bytes (WWN) in the array to represent a
+ FC target.
+ @param Lun The LUN of the SCSI device for which a device path node is to be
+ allocated and built.
+ @param DevicePath A pointer to a single device path node that describes the SCSI device
+ specified by Target and Lun. This function is responsible for
+ allocating the buffer DevicePath with the boot service
+ AllocatePool(). It is the caller's responsibility to free
+ DevicePath when the caller is finished with DevicePath.
+
+ @retval EFI_SUCCESS The device path node that describes the SCSI device specified by
+ Target and Lun was allocated and returned in
+ DevicePath.
+ @retval EFI_INVALID_PARAMETER DevicePath is NULL.
+ @retval EFI_NOT_FOUND The SCSI devices specified by Target and Lun does not exist
+ on the SCSI channel.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate DevicePath.
+
+**/
+EFI_STATUS
+EFIAPI
+ExtScsiPassThruBuildDevicePath (
+ IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This,
+ IN UINT8 *Target,
+ IN UINT64 Lun,
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
+ )
+{
+ EFI_DEV_PATH *DevicePathNode;
+ ATA_ATAPI_PASS_THRU_INSTANCE *Instance;
+ UINT8 Port;
+ UINT8 PortMultiplier;
+
+ Instance = EXT_SCSI_PASS_THRU_PRIVATE_DATA_FROM_THIS (This);
+
+ Port = Target[0];
+ PortMultiplier = Target[1];
+
+ //
+ // Validate parameters passed in.
+ //
+ if (DevicePath == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // can not build device path for the SCSI Host Controller.
+ //
+ if (Lun != 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ if (SearchDeviceInfoList(Instance, Port, PortMultiplier, EfiIdeCdrom) == NULL) {
+ return EFI_NOT_FOUND;
+ }
+
+ DevicePathNode = AllocateCopyPool (sizeof (SATA_DEVICE_PATH), &mSataDevicePathTemplate);
+ if (DevicePathNode == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ DevicePathNode->Sata.HBAPortNumber = Port;
+ DevicePathNode->Sata.PortMultiplierPortNumber = PortMultiplier;
+ DevicePathNode->Sata.Lun = (UINT16) Lun;
+
+ *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) DevicePathNode;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Used to translate a device path node to a Target ID and LUN.
+
+ @param This A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance.
+ @param DevicePath A pointer to a single device path node that describes the SCSI device
+ on the SCSI channel.
+ @param Target A pointer to the Target Array which represents the ID of a SCSI device
+ on the SCSI channel.
+ @param Lun A pointer to the LUN of a SCSI device on the SCSI channel.
+
+ @retval EFI_SUCCESS DevicePath was successfully translated to a Target ID and
+ LUN, and they were returned in Target and Lun.
+ @retval EFI_INVALID_PARAMETER DevicePath or Target or Lun is NULL.
+ @retval EFI_NOT_FOUND A valid translation from DevicePath to a Target ID and LUN
+ does not exist.
+ @retval EFI_UNSUPPORTED This driver does not support the device path node type in
+ DevicePath.
+
+**/
+EFI_STATUS
+EFIAPI
+ExtScsiPassThruGetTargetLun (
+ IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ OUT UINT8 **Target,
+ OUT UINT64 *Lun
+ )
+{
+ EFI_DEV_PATH *DevicePathNode;
+ ATA_ATAPI_PASS_THRU_INSTANCE *Instance;
+ LIST_ENTRY *Node;
+
+ Instance = EXT_SCSI_PASS_THRU_PRIVATE_DATA_FROM_THIS (This);
+
+ //
+ // Validate parameters passed in.
+ //
+ if (DevicePath == NULL || Target == NULL || Lun == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (*Target == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ //
+ // Check whether the DevicePath belongs to SCSI_DEVICE_PATH
+ //
+ if ((DevicePath->Type != MESSAGING_DEVICE_PATH) ||
+ ((DevicePath->SubType != MSG_ATAPI_DP) &&
+ (DevicePath->SubType != MSG_SATA_DP)) ||
+ ((DevicePathNodeLength(DevicePath) != sizeof(ATAPI_DEVICE_PATH)) &&
+ (DevicePathNodeLength(DevicePath) != sizeof(SATA_DEVICE_PATH)))) {
+ return EFI_UNSUPPORTED;
+ }
+
+ SetMem (*Target, TARGET_MAX_BYTES, 0xFF);
+
+ DevicePathNode = (EFI_DEV_PATH *) DevicePath;
+
+ (*Target)[0] = (UINT8) DevicePathNode->Sata.HBAPortNumber;
+ (*Target)[1] = (UINT8) DevicePathNode->Sata.PortMultiplierPortNumber;
+ *Lun = (UINT8) DevicePathNode->Sata.Lun;
+
+ Node = SearchDeviceInfoList(Instance, (*Target)[0], (*Target)[1], EfiIdeCdrom);
+
+ if (Node == NULL) {
+ return EFI_NOT_FOUND;
+ }
+
+ if (*Lun != 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Resets a SCSI channel. This operation resets all the SCSI devices connected to the SCSI channel.
+
+ @param This A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The SCSI channel was reset.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to reset the SCSI channel.
+ @retval EFI_TIMEOUT A timeout occurred while attempting to reset the SCSI channel.
+ @retval EFI_UNSUPPORTED The SCSI channel does not support a channel reset operation.
+
+**/
+EFI_STATUS
+EFIAPI
+ExtScsiPassThruResetChannel (
+ IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Resets a SCSI logical unit that is connected to a SCSI channel.
+
+ @param This A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance.
+ @param Target The Target is an array of size TARGET_MAX_BYTE and it represents the
+ target port ID of the SCSI device containing the SCSI logical unit to
+ reset. Transport drivers may chose to utilize a subset of this array to suit
+ the representation of their targets.
+ @param Lun The LUN of the SCSI device to reset.
+
+ @retval EFI_SUCCESS The SCSI device specified by Target and Lun was reset.
+ @retval EFI_INVALID_PARAMETER Target or Lun is NULL.
+ @retval EFI_TIMEOUT A timeout occurred while attempting to reset the SCSI device
+ specified by Target and Lun.
+ @retval EFI_UNSUPPORTED The SCSI channel does not support a target reset operation.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to reset the SCSI device
+ specified by Target and Lun.
+
+**/
+EFI_STATUS
+EFIAPI
+ExtScsiPassThruResetTargetLun (
+ IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This,
+ IN UINT8 *Target,
+ IN UINT64 Lun
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Used to retrieve the list of legal Target IDs for SCSI devices on a SCSI channel. These can either
+ be the list SCSI devices that are actually present on the SCSI channel, or the list of legal Target IDs
+ for the SCSI channel. Regardless, the caller of this function must probe the Target ID returned to
+ see if a SCSI device is actually present at that location on the SCSI channel.
+
+ @param This A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance.
+ @param Target (TARGET_MAX_BYTES) of a SCSI device present on the SCSI channel.
+ On output, a pointer to the Target ID (an array of
+ TARGET_MAX_BYTES) of the next SCSI device present on a SCSI
+ channel. An input value of 0xF(all bytes in the array are 0xF) in the
+ Target array retrieves the Target ID of the first SCSI device present on a
+ SCSI channel.
+
+ @retval EFI_SUCCESS The Target ID of the next SCSI device on the SCSI
+ channel was returned in Target.
+ @retval EFI_INVALID_PARAMETER Target or Lun is NULL.
+ @retval EFI_TIMEOUT Target array is not all 0xF, and Target was not
+ returned on a previous call to GetNextTarget().
+ @retval EFI_NOT_FOUND There are no more SCSI devices on this SCSI channel.
+
+**/
+EFI_STATUS
+EFIAPI
+ExtScsiPassThruGetNextTarget (
+ IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This,
+ IN OUT UINT8 **Target
+ )
+{
+ ATA_ATAPI_PASS_THRU_INSTANCE *Instance;
+ LIST_ENTRY *Node;
+ EFI_ATA_DEVICE_INFO *DeviceInfo;
+ UINT8 *Target8;
+ UINT16 *Target16;
+
+ Instance = EXT_SCSI_PASS_THRU_PRIVATE_DATA_FROM_THIS (This);
+
+ if (Target == NULL || *Target == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Target8 = *Target;
+ Target16 = (UINT16 *)*Target;
+
+ if (CompareMem(Target8, mScsiId, TARGET_MAX_BYTES) != 0) {
+ //
+ // For ATAPI device, we use 2 least significant bytes to represent the location of SCSI device.
+ // So the higher bytes in Target array should be 0xFF.
+ //
+ if (CompareMem (&Target8[2], &mScsiId[2], TARGET_MAX_BYTES - 2) != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // When Target is not all 0xFF's, compare 2 least significant bytes with
+ // previous target id to see if it is returned by previous call.
+ //
+ if (*Target16 != Instance->PreviousTargetId) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Traverse the whole device list to find the next cdrom closed to
+ // the device signified by Target[0] and Target[1].
+ //
+ // Note that we here use a tricky way to find the next cdrom :
+ // All ata devices are detected and inserted into the device list
+ // sequentially.
+ //
+ Node = GetFirstNode (&Instance->DeviceList);
+ while (!IsNull (&Instance->DeviceList, Node)) {
+ DeviceInfo = ATA_ATAPI_DEVICE_INFO_FROM_THIS (Node);
+
+ if ((DeviceInfo->Type == EfiIdeCdrom) &&
+ ((Target8[0] < DeviceInfo->Port) ||
+ ((Target8[0] == DeviceInfo->Port) &&
+ (Target8[1] < DeviceInfo->PortMultiplier)))) {
+ Target8[0] = (UINT8)DeviceInfo->Port;
+ Target8[1] = (UINT8)DeviceInfo->PortMultiplier;
+ goto Exit;
+ }
+
+ Node = GetNextNode (&Instance->DeviceList, Node);
+ }
+
+ return EFI_NOT_FOUND;
+ } else {
+ //
+ // If the array is all 0xFF's, start to traverse the device list from the beginning
+ //
+ Node = GetFirstNode (&Instance->DeviceList);
+
+ while (!IsNull (&Instance->DeviceList, Node)) {
+ DeviceInfo = ATA_ATAPI_DEVICE_INFO_FROM_THIS (Node);
+
+ if (DeviceInfo->Type == EfiIdeCdrom) {
+ Target8[0] = (UINT8)DeviceInfo->Port;
+ Target8[1] = (UINT8)DeviceInfo->PortMultiplier;
+ goto Exit;
+ }
+
+ Node = GetNextNode (&Instance->DeviceList, Node);
+ }
+
+ return EFI_NOT_FOUND;
+ }
+
+Exit:
+ //
+ // Update the PreviousTargetId.
+ //
+ Instance->PreviousTargetId = *Target16;
+
+ return EFI_SUCCESS;
+}
diff --git a/Platforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.h b/Platforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.h
new file mode 100755
index 0000000..52eec81
--- /dev/null
+++ b/Platforms/APM/XGene/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.h
@@ -0,0 +1,1152 @@
+/** @file
+ Header file for ATA/ATAPI PASS THRU driver.
+
+ Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __ATA_ATAPI_PASS_THRU_H__
+#define __ATA_ATAPI_PASS_THRU_H__
+
+#include <Uefi.h>
+
+#include <IndustryStandard/Atapi.h>
+#include <IndustryStandard/Scsi.h>
+
+#include <Protocol/AtaPassThru.h>
+#include <Protocol/ScsiPassThruExt.h>
+#include <Protocol/IdeControllerInit.h>
+
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/PciLib.h>
+#include <Library/PcdLib.h>
+#include <Library/TimerLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Library/DevicePathLib.h>
+
+#include "AhciMode.h"
+
+extern EFI_DRIVER_BINDING_PROTOCOL gAtaAtapiPassThruDriverBinding;
+extern EFI_COMPONENT_NAME_PROTOCOL gAtaAtapiPassThruComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gAtaAtapiPassThruComponentName2;
+
+#define ATA_ATAPI_PASS_THRU_SIGNATURE SIGNATURE_32 ('a', 'a', 'p', 't')
+#define ATA_ATAPI_DEVICE_SIGNATURE SIGNATURE_32 ('a', 'd', 'e', 'v')
+#define ATA_NONBLOCKING_TASK_SIGNATURE SIGNATURE_32 ('a', 't', 's', 'k')
+
+typedef struct _ATA_NONBLOCK_TASK ATA_NONBLOCK_TASK;
+
+typedef struct {
+ UINT32 RegionBaseAddr;
+ UINT16 ByteCount;
+ UINT16 EndOfTable;
+} EFI_ATA_DMA_PRD;
+
+typedef struct {
+ UINT8 ModeNumber : 3;
+ UINT8 ModeCategory : 5;
+} EFI_ATA_TRANSFER_MODE;
+
+typedef enum {
+ EfiAtaIdeMode,
+ EfiAtaAhciMode,
+ EfiAtaRaidMode,
+ EfiAtaUnknownMode
+} EFI_ATA_HC_WORK_MODE;
+
+typedef enum {
+ EfiIdeCdrom, /* ATAPI CDROM */
+ EfiIdeHarddisk, /* Hard Disk */
+ EfiPortMultiplier, /* Port Multiplier */
+ EfiIdeUnknown
+} EFI_ATA_DEVICE_TYPE;
+
+//
+// Ahci mode device info
+//
+typedef struct {
+ UINT32 Signature;
+ LIST_ENTRY Link;
+
+ UINT16 Port;
+ UINT16 PortMultiplier;
+ EFI_ATA_DEVICE_TYPE Type;
+
+ EFI_IDENTIFY_DATA *IdentifyData;
+} EFI_ATA_DEVICE_INFO;
+
+typedef struct {
+ UINT32 Signature;
+
+ EFI_HANDLE ControllerHandle;
+
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeControllerInit;
+
+ EFI_ATA_PASS_THRU_MODE AtaPassThruMode;
+ EFI_ATA_PASS_THRU_PROTOCOL AtaPassThru;
+
+ EFI_EXT_SCSI_PASS_THRU_MODE ExtScsiPassThruMode;
+ EFI_EXT_SCSI_PASS_THRU_PROTOCOL ExtScsiPassThru;
+
+ EFI_ATA_HC_WORK_MODE Mode;
+
+ EFI_AHCI_REGISTERS AhciRegisters;
+
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+ //
+ // The attached device list
+ //
+ LIST_ENTRY DeviceList;
+
+ //
+ // For AtaPassThru protocol, using the following bytes to record the previous call in
+ // GetNextPort()/GetNextDevice().
+ //
+ UINT16 PreviousPort;
+ UINT16 PreviousPortMultiplier;
+
+ //
+ // For ExtScsiPassThru protocol, using the following bytes to record the previous call in
+ // GetNextTarget()/GetNextTargetLun().
+ //
+ UINT16 PreviousTargetId;
+ UINT64 PreviousLun;
+
+ //
+ // For Non-blocking.
+ //
+ EFI_EVENT TimerEvent;
+ LIST_ENTRY NonBlockingTaskList;
+} ATA_ATAPI_PASS_THRU_INSTANCE;
+
+//
+// Task for Non-blocking mode.
+//
+struct _ATA_NONBLOCK_TASK {
+ UINT32 Signature;
+ LIST_ENTRY Link;
+
+ UINT16 Port;
+ UINT16 PortMultiplier;
+ EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet;
+ BOOLEAN IsStart;
+ EFI_EVENT Event;
+ UINT64 RetryTimes;
+ VOID *Map; // Pointer to map.
+ VOID *TableMap;// Pointer to PRD table map.
+ EFI_ATA_DMA_PRD *MapBaseAddress; // Pointer to range Base address for Map.
+};
+
+//
+// Timeout value which uses 100ns as a unit.
+// It means 3 second span.
+//
+#define ATA_ATAPI_TIMEOUT EFI_TIMER_PERIOD_SECONDS(3)
+
+#define IS_ALIGNED(addr, size) (((UINTN) (addr) & (size - 1)) == 0)
+
+#define ATA_PASS_THRU_PRIVATE_DATA_FROM_THIS(a) \
+ CR (a, \
+ ATA_ATAPI_PASS_THRU_INSTANCE, \
+ AtaPassThru, \
+ ATA_ATAPI_PASS_THRU_SIGNATURE \
+ )
+
+#define EXT_SCSI_PASS_THRU_PRIVATE_DATA_FROM_THIS(a) \
+ CR (a, \
+ ATA_ATAPI_PASS_THRU_INSTANCE, \
+ ExtScsiPassThru, \
+ ATA_ATAPI_PASS_THRU_SIGNATURE \
+ )
+
+
+#define ATA_ATAPI_DEVICE_INFO_FROM_THIS(a) \
+ CR (a, \
+ EFI_ATA_DEVICE_INFO, \
+ Link, \
+ ATA_ATAPI_DEVICE_SIGNATURE \
+ );
+
+#define ATA_NON_BLOCK_TASK_FROM_ENTRY(a) \
+ CR (a, \
+ ATA_NONBLOCK_TASK, \
+ Link, \
+ ATA_NONBLOCKING_TASK_SIGNATURE \
+ );
+
+/**
+ Retrieves a Unicode string that is the user readable name of the driver.
+
+ This function retrieves the user readable name of a driver in the form of a
+ Unicode string. If the driver specified by This has a user readable name in
+ the language specified by Language, then a pointer to the driver name is
+ returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+ by This does not support the language specified by Language,
+ then EFI_UNSUPPORTED is returned.
+
+ @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+ EFI_COMPONENT_NAME_PROTOCOL instance.
+
+ @param Language[in] A pointer to a Null-terminated ASCII string
+ array indicating the language. This is the
+ language of the driver name that the caller is
+ requesting, and it must match one of the
+ languages specified in SupportedLanguages. The
+ number of languages supported by a driver is up
+ to the driver writer. Language is specified
+ in RFC 4646 or ISO 639-2 language code format.
+
+ @param DriverName[out] A pointer to the Unicode string to return.
+ This Unicode string is the name of the
+ driver specified by This in the language
+ specified by Language.
+
+ @retval EFI_SUCCESS The Unicode string for the Driver specified by
+ This and the language specified by Language was
+ returned in DriverName.
+
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+
+ @retval EFI_INVALID_PARAMETER DriverName is NULL.
+
+ @retval EFI_UNSUPPORTED The driver specified by This does not support
+ the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+AtaAtapiPassThruComponentNameGetDriverName (
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
+ );
+
+/**
+ Retrieves a Unicode string that is the user readable name of the controller
+ that is being managed by a driver.
+
+ This function retrieves the user readable name of the controller specified by
+ ControllerHandle and ChildHandle in the form of a Unicode string. If the
+ driver specified by This has a user readable name in the language specified by
+ Language, then a pointer to the controller name is returned in ControllerName,
+ and EFI_SUCCESS is returned. If the driver specified by This is not currently
+ managing the controller specified by ControllerHandle and ChildHandle,
+ then EFI_UNSUPPORTED is returned. If the driver specified by This does not
+ support the language specified by Language, then EFI_UNSUPPORTED is returned.
+
+ @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+ EFI_COMPONENT_NAME_PROTOCOL instance.
+
+ @param ControllerHandle[in] The handle of a controller that the driver
+ specified by This is managing. This handle
+ specifies the controller whose name is to be
+ returned.
+
+ @param ChildHandle[in] The handle of the child controller to retrieve
+ the name of. This is an optional parameter that
+ may be NULL. It will be NULL for device
+ drivers. It will also be NULL for a bus drivers
+ that wish to retrieve the name of the bus
+ controller. It will not be NULL for a bus
+ driver that wishes to retrieve the name of a
+ child controller.
+
+ @param Language[in] A pointer to a Null-terminated ASCII string
+ array indicating the language. This is the
+ language of the driver name that the caller is
+ requesting, and it must match one of the
+ languages specified in SupportedLanguages. The
+ number of languages supported by a driver is up
+ to the driver writer. Language is specified in
+ RFC 4646 or ISO 639-2 language code format.
+
+ @param ControllerName[out] A pointer to the Unicode string to return.
+ This Unicode string is the name of the
+ controller specified by ControllerHandle and
+ ChildHandle in the language specified by
+ Language from the point of view of the driver
+ specified by This.
+
+ @retval EFI_SUCCESS The Unicode string for the user readable name in
+ the language specified by Language for the
+ driver specified by This was returned in
+ DriverName.
+
+ @retval EFI_