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authorLeif Lindholm <leif.lindholm@linaro.org>2015-04-21 15:27:27 +0100
committerLeif Lindholm <leif.lindholm@linaro.org>2015-05-11 12:05:12 +0100
commit8dc105079d3242a0352c726994cbedd172111111 (patch)
treee7a65bcea91b89a5ef277c933a98d0ee457d9a1c
parent0c1c017e008ffda2313af6f383b8c364bea5511e (diff)
downloadOpenPlatformPkg-8dc105079d3242a0352c726994cbedd172111111.tar.gz
FVP ACPI tables.
-rw-r--r--Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf32
-rw-r--r--Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl209
-rw-r--r--Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/dsdt.asl144
-rw-r--r--Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/facp.asl197
-rw-r--r--Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl116
5 files changed, 698 insertions, 0 deletions
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf
new file mode 100644
index 0000000..c851d12
--- /dev/null
+++ b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf
@@ -0,0 +1,32 @@
+##
+# Component description file for PlatformAcpiTables module.
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2013, Linaro Ltd.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformAcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ apic.asl
+ dsdt.asl
+ facp.asl
+ gtdt.asl
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl
new file mode 100644
index 0000000..f94686e
--- /dev/null
+++ b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone@linaro.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * NB: This License is also known as the "BSD 2-Clause License".
+ *
+ *
+ * [APIC] Multiple APIC Description Table (MADT)
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ */
+
+[0004] Signature : "APIC"
+[0004] Table Length : 00000000
+[0001] Revision : 04
+[0001] Checksum : 00
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110623
+
+[0004] Local Apic Address : 2C000000
+[0004] Flags (decoded below) : 00000000
+ PC-AT Compatibility : 0
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 4C
+[0002] Reserved : 0000
+[0004] CPU Interface Number : 00000000
+[0004] Processor UID : 00000000
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C000000 /* armv8 FVP Base GIC address */
+[0008] Virtual GIC Base Address : 0
+[0008] Hypervisor GIC Base Address : 0
+[0004] Virtual GIC Interrupt : 0
+[0008] Redistributor Base Address : 0
+[0008] ARM MPIDR : 0
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 4C
+[0002] Reserved : 0000
+[0004] CPU Interface Number : 00000001
+[0004] Processor UID : 00000001
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C000000
+[0008] Virtual GIC Base Address : 0
+[0008] Hypervisor GIC Base Address : 0
+[0004] Virtual GIC Interrupt : 0
+[0008] Redistributor Base Address : 0
+[0008] ARM MPIDR : 0000000000000001
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 4C
+[0002] Reserved : 0000
+[0004] CPU Interface Number : 00000002
+[0004] Processor UID : 00000002
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C000000
+[0008] Virtual GIC Base Address : 0
+[0008] Hypervisor GIC Base Address : 0
+[0004] Virtual GIC Interrupt : 0
+[0008] Redistributor Base Address : 0
+[0008] ARM MPIDR : 0000000000000002
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 4C
+[0002] Reserved : 0000
+[0004] CPU Interface Number : 00000003
+[0004] Processor UID : 00000003
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C000000
+[0008] Virtual GIC Base Address : 0
+[0008] Hypervisor GIC Base Address : 0
+[0004] Virtual GIC Interrupt : 0
+[0008] Redistributor Base Address : 0
+[0008] ARM MPIDR : 0000000000000003
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 4C
+[0002] Reserved : 0000
+[0004] CPU Interface Number : 00000004
+[0004] Processor UID : 00000004
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C000000
+[0008] Virtual GIC Base Address : 0
+[0008] Hypervisor GIC Base Address : 0
+[0004] Virtual GIC Interrupt : 0
+[0008] Redistributor Base Address : 0
+[0008] ARM MPIDR : 0000000000000100
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 4C
+[0002] Reserved : 0000
+[0004] CPU Interface Number : 00000005
+[0004] Processor UID : 00000005
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C000000
+[0008] Virtual GIC Base Address : 0
+[0008] Hypervisor GIC Base Address : 0
+[0004] Virtual GIC Interrupt : 0
+[0008] Redistributor Base Address : 0
+[0008] ARM MPIDR : 0000000000000101
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 4C
+[0002] Reserved : 0000
+[0004] CPU Interface Number : 00000006
+[0004] Processor UID : 00000006
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C000000
+[0008] Virtual GIC Base Address : 0
+[0008] Hypervisor GIC Base Address : 0
+[0004] Virtual GIC Interrupt : 0
+[0008] Redistributor Base Address : 0
+[0008] ARM MPIDR : 0000000000000102
+
+[0001] Subtable Type : 0B [Generic Interrupt Controller]
+[0001] Length : 4C
+[0002] Reserved : 0000
+[0004] CPU Interface Number : 00000007
+[0004] Processor UID : 00000007
+[0004] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[0004] Parking Protocol Version : 00000000
+[0004] Performance Interrupt : 00000000
+[0008] Parked Address : 0000000000000000
+[0008] Base Address : 000000002C000000
+[0008] Virtual GIC Base Address : 0
+[0008] Hypervisor GIC Base Address : 0
+[0004] Virtual GIC Interrupt : 0
+[0008] Redistributor Base Address : 0
+[0008] ARM MPIDR : 0000000000000103
+
+[0001] Subtable Type : 0C [Generic Interrupt Distributor]
+[0001] Length : 18
+[0002] Reserved : 0000
+[0004] Local GIC Hardware ID : 00000000
+[0008] Base Address : 000000002F000000 /* armv8 FVP Base GIC distributor base addr */
+[0004] Interrupt Base : 00000000
+[0004] Reserved : 00000000
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/dsdt.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/dsdt.asl
new file mode 100644
index 0000000..172ca3a
--- /dev/null
+++ b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/dsdt.asl
@@ -0,0 +1,144 @@
+/*
+* Copyright (c) 2013, Al Stone <al.stone@linaro.org>
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*
+* NB: This License is also known as the "BSD 2-Clause License".
+*
+*
+* [DSDT] Description of the armv8 VE Model
+*
+*/
+
+DefinitionBlock (
+ "dsdt.aml", // output filename
+ "DSDT", // table signature
+ 2, // DSDT compliance revision
+ "LINARO", // OEM ID
+ "RTSMVEV8", // table ID
+ 0x00000004) // OEM revision
+{
+ Scope (\_SB)
+ {
+ Method (_OSC, 4, NotSerialized)
+ {
+ /* Platform-Wide OSPM Capabilities */
+ If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")))
+ {
+ /* APEI support unconditionally */
+ Return (Arg3)
+ } Else {
+ CreateDWordField (Arg3, Zero, CDW1)
+ /* Set invalid UUID error bit */
+ Or (CDW1, 0x04, CDW1)
+ Return (Arg3)
+ }
+ }
+
+ //
+ // Two Emulated aarch64 CPUs each with 4 cores
+ //
+ Device(CPU0) { // Cluster 0, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0)
+ }
+ Device(CPU1) { // Cluster 0, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 1)
+ }
+ Device(CPU2) { // Cluster 0, Cpu 2
+ Name(_HID, "ACPI0007")
+ Name(_UID, 2)
+ }
+ Device(CPU3) { // Cluster 0, Cpu 3
+ Name(_HID, "ACPI0007")
+ Name(_UID, 3)
+ }
+ Device(CPU4) { // Cluster 1, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 4)
+ }
+ Device(CPU5) { // Cluster 1, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 5)
+ }
+ Device(CPU6) { // Cluster 1, Cpu 2
+ Name(_HID, "ACPI0007")
+ Name(_UID, 6)
+ }
+ Device(CPU7) { // Cluster 1, Cpu 3
+ Name(_HID, "ACPI0007")
+ Name(_UID, 7)
+ }
+
+ // SMC91X
+ Device (NET0) {
+ Name (_HID, "LNRO0003")
+ Name (_UID, 0)
+
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x1a000000, 0x00010000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {0x2F}
+ })
+ }
+
+ // SYSREG
+ Device (SREG) {
+ Name (_HID, "LNRO0009")
+ Name (_UID, 0)
+
+ Method (_CRS, 0x0, Serialized) {
+ Name (RBUF, ResourceTemplate() {
+ Memory32Fixed (ReadWrite, 0x1c010000, 0x1000)
+ })
+ Return (RBUF)
+ }
+ }
+
+ // VIRTIO
+ Device (VIRT) {
+ Name (_HID, "LNRO0005")
+ Name (_UID, 0)
+
+ Name (_CRS, ResourceTemplate() {
+ Memory32Fixed (ReadWrite, 0x1c130000, 0x1000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x4A}
+ })
+ }
+
+ // UART PL011
+ Device(COM0) {
+ Name(_HID, "ARMH0011")
+ Name(_CID, "PL011")
+ Name(_UID, Zero)
+
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1c090000, 0x1000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 0x25 }
+ })
+ }
+ }
+}
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/facp.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/facp.asl
new file mode 100644
index 0000000..c288ae2
--- /dev/null
+++ b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/facp.asl
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone@linaro.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * NB: This License is also known as the "BSD 2-Clause License".
+ *
+ *
+ * [FACP] ACPI Table
+ *
+ */
+
+[0004] Signature : "FACP"
+[0004] Table Length : 0000010C
+[0001] Revision : 05
+[0001] Checksum : 18
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20111123
+
+[0004] FACS Address : 00000000
+[0004] DSDT Address : 00000010
+[0001] Model : 00
+[0001] PM Profile : 04 /* Enterprise Server */
+[0002] SCI Interrupt : 0000
+[0004] SMI Command Port : 00000000
+[0001] ACPI Enable Value : 00
+[0001] ACPI Disable Value : 00
+[0001] S4BIOS Command : 00
+[0001] P-State Control : 00
+[0004] PM1A Event Block Address : 00000001
+[0004] PM1B Event Block Address : 00000000
+[0004] PM1A Control Block Address : 00000001
+[0004] PM1B Control Block Address : 00000000
+[0004] PM2 Control Block Address : 00000001
+[0004] PM Timer Block Address : 00000001
+[0004] GPE0 Block Address : 00000001
+[0004] GPE1 Block Address : 00000000
+[0001] PM1 Event Block Length : 04
+[0001] PM1 Control Block Length : 02
+[0001] PM2 Control Block Length : 01
+[0001] PM Timer Block Length : 04
+[0001] GPE0 Block Length : 08
+[0001] GPE1 Block Length : 00
+[0001] GPE1 Base Offset : 00
+[0001] _CST Support : 00
+[0002] C2 Latency : 0000
+[0002] C3 Latency : 0000
+[0002] CPU Cache Size : 0000
+[0002] Cache Flush Stride : 0000
+[0001] Duty Cycle Offset : 00
+[0001] Duty Cycle Width : 00
+[0001] RTC Day Alarm Index : 00
+[0001] RTC Month Alarm Index : 00
+[0001] RTC Century Index : 00
+[0002] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[0001] Reserved : 00
+[0004] Flags (decoded below) : 00000000
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 1
+ All CPUs support C1 (V1) : 0
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 1
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 0
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 0
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 1
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 0
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 1
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 1
+ Low Power S0 Idle (V5) : 1
+
+[0012] Reset Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000001
+
+[0001] Value to cause reset : 00
+[0002] ARM_BOOT_ARCH (decoded below) : 0001
+ Use PSCI 0.2+ : 1
+ PSCI Use HVC : 0
+[0001] FADT Minor Revision : 01
+[0008] FACS Address : 0000000000000000
+[0008] DSDT Address : 0000000000000010
+[0012] PM1A Event Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 20
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 02 [Word Access:16]
+[0008] Address : 0000000000000001
+
+[0012] PM1B Event Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0012] PM1A Control Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 10
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 02 [Word Access:16]
+[0008] Address : 0000000000000001
+
+[0012] PM1B Control Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+[0012] PM2 Control Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000001
+
+[0012] PM Timer Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 20
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 03 [DWord Access:32]
+[0008] Address : 0000000000000001
+
+[0012] GPE0 Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 80
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000001
+
+[0012] GPE1 Block : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 00
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 00 [Undefined/Legacy]
+[0008] Address : 0000000000000000
+
+
+[0012] Sleep Control Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000000
+
+[0012] Sleep Status Register : [Generic Address Structure]
+[0001] Space ID : 01 [SystemIO]
+[0001] Bit Width : 08
+[0001] Bit Offset : 00
+[0001] Encoded Access Width : 01 [Byte Access:8]
+[0008] Address : 0000000000000000
+
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl
new file mode 100644
index 0000000..d304243
--- /dev/null
+++ b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone@linaro.org>
+ * Hanjun Guo <hanjun.guo@linaro.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * NB: This License is also known as the "BSD 2-Clause License".
+ *
+ *
+ * [GTDT] Generic Timer Description Table
+ * Format: [ByteLength] FieldName : HexFieldValue
+ *
+ */
+
+[0004] Signature : "GTDT"
+[0004] Table Length : 00000050
+[0001] Revision : 02
+[0001] Checksum : F1
+[0006] Oem ID : "LINARO"
+[0008] Oem Table ID : "RTSMVEV8"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20110623
+
+[0008] Counter Block Address : 0000000000000000
+[0004] Reserved : 00000000
+
+/* In RTSM model's dts file, the last cell of interrupts
+ * is 0xff01, it means its cpu mask is FF, and trigger type
+ * and flag is 1 = low-to-high edge triggered.
+ *
+ * so in ACPI the Trigger Mode is 1 - Edge triggered, and
+ * Polarity is 0 - Active high as ACPI spec describled.
+ *
+ * using direct mapping for hwirqs, it means that we using
+ * ID [16, 31] for PPI, not [0, 15] used in FDT.
+ */
+[0004] Secure EL1 Interrupt : 0000001d
+[0004] SEL1 Flags (decoded below) : 00000001
+ Trigger Mode : 1
+ Polarity : 0
+ Always-on : 0
+
+[0004] Non-Secure EL1 Interrupt : 0000001e
+[0004] NSEL1 Flags (decoded below) : 00000001
+ Trigger Mode : 1
+ Polarity : 0
+ Always-on : 0
+
+[0004] Virtual Timer Interrupt : 0000001b
+[0004] VT Flags (decoded below) : 00000001
+ Trigger Mode : 1
+ Polarity : 0
+ Always-on : 0
+
+[0004] Non-Secure EL2 Interrupt : 0000001a
+[0004] NSEL2 Flags (decoded below) : 00000001
+ Trigger Mode : 1
+ Polarity : 0
+ Always-on : 0
+
+/* The 64-bit physical address at which the Counter Read block is located */
+[0008] CntReadBase Physical address : 0000000000000000
+
+[0004] Platform Timer Count : 00000001
+[0004] Platform Timer Offset : 0000005C
+
+/* Memory-mapped GT (Generic Timer) structures */
+[0001] Subtable Type : 00
+[0002] Length : 0064
+[0001] Reserved : 000000
+[0008] Block Address : 000000002a810000
+[0004] Timer Count : 00000001
+[0004] Timer Offset : 00000010
+
+/* One frame is available */
+[0001] Frame Number : 00
+[0003] Reserved : 000000
+[0008] Base Address : 000000002a820000
+[0008] EL0 Base Address : FFFFFFFFFFFFFFFF
+[0004] Timer Interrupt : 00000029 /* 25+16 */
+[0004] Timer Flags (decoded below) : 00000000 /* Active high level-sensitive */
+ Trigger Mode : 0
+ Polarity : 0
+/* No virtual timer */
+[0004] Virtual Timer Interrupt : 00000000
+[0004] Virtual Timer Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+[0004] Common Flags (decoded below) : 00000000
+ Secure : 0
+ Always On : 0
+