tag namedrm/tegra/for-3.17-rc1 (37f31b2775fe4bf54e483e7d618adead0f518d88)
tag date2014-08-06 17:14:57 +0200
tagged byThierry Reding <>
tagged objectcommit ef70728c7a...
drm/tegra: Changes for v3.17-rc1
Mostly some cleanup all over the place. Pitch alignment limitations of the display controller are now honored and job submission is 64-bit safe. The SOR output (used for eDP) properly configures sync signal polarities according to the display mode rather than hard-coding them to some value and the number of bits per color is now taken from the panel rather than hard-coded to properly support 24-bit vs. 18-bit panels. The DSI controller now properly supports non-continuous clock mode. GEM objects can now have their flags and tiling mode modified via IOCTLs to allow buffers imported from Nouveau to be properly displayed. Newer generations of the Tegra display controller can also detile block linear buffers at scan-out time. Finally the driver now properly exports MODULE_DEVICE_TABLEs to allow it to be automatically loaded when built as a module. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJT4kgqAAoJEN0jrNd/PrOhwSUP/ja3Szs8mdKzRtDcmUla7pIU g6dVTrXibruWQtB4Mf0Zv/7vVHDAuVW3q01lRHamud9g+Ci74YDsd99AJuguBQqy m0wNm2GFye64pcc/QdpmpH6zUEtt/eULxKYWco3jxGaMtH+v051qIyXE7JhS2KNo vE0XUV6bQPQWfhBr94IqJL79lO/DaNOKYuGATh3g6o/D/R+EFjNod7vZ7wGjpzoG LFqCsTfMA80sv/S19GLCwX/m/DbVVjPHPl1AxRNz5KhWXguo+teQ+0hKJ3t635IE xkW9GJ5Ghuq524sLNY+kEwAiuGVOotFIFqy9lPFNQllp7tyyK0uaWaQHbINYPso9 3QW4qdGfoioYzg6OzpLMQLwiHwl37z9oaDRodb+tZr9DGfrZ2GihTJwZIqLezBhD KGwDUb6/mexuotn6bg3QavFGgGKxrzb/rmiC/o4wJie6gSw3fJLzhOs1fgcus5p8 NcSRWkl90wbuoVE2h9I3mdHi4A+dAkAR9K6e8UxQCGfJwfisSeYABqh/UvRxNs3u mp8fIBbEmUKr6Kznaehw6VBy4xd6yp6hpjMJjPClNS4oErXuzhvZdoKjma7Jg6wj 7KFNSs1R1euNRjRX2J7ITPz7sIkjac5Ms2ejeniG5+RpqWp4c54G2MxuhvbFlVEA GOZYuKjSn6IEOkR5cx/X =qYgE -----END PGP SIGNATURE-----