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authorLen Brown <len.brown@intel.com>2013-02-27 13:18:50 -0500
committerLen Brown <len.brown@intel.com>2013-04-17 19:23:32 -0400
commit86239ceb33b0d8480b0f0ca0eec08e7f7a807374 (patch)
treea550318b207a3bdde7c095b23c3dfef18637ea12 /drivers/idle
parentca58710f3ae585ed6203043cc6d4ffb805adeee4 (diff)
downloadkernel-86239ceb33b0d8480b0f0ca0eec08e7f7a807374.tar.gz
intel_idle: initial C8, C9, C10 support
Allow intel_idle and cpuidle to utilize C8, C9, C10 when they are present on... "Fourth Generation Intel(R) Core(TM) Processors", which are based on Intel(R) microarchitecture code name Haswell. Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'drivers/idle')
-rw-r--r--drivers/idle/intel_idle.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 1a38dd7dfe4e..c7fbac392952 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -274,6 +274,27 @@ static struct cpuidle_state hsw_cstates[CPUIDLE_STATE_MAX] = {
.target_residency = 500,
.enter = &intel_idle },
{
+ .name = "C8-HSW",
+ .desc = "MWAIT 0x40",
+ .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 300,
+ .target_residency = 900,
+ .enter = &intel_idle },
+ {
+ .name = "C9-HSW",
+ .desc = "MWAIT 0x50",
+ .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 600,
+ .target_residency = 1800,
+ .enter = &intel_idle },
+ {
+ .name = "C10-HSW",
+ .desc = "MWAIT 0x60",
+ .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 2600,
+ .target_residency = 7700,
+ .enter = &intel_idle },
+ {
.enter = NULL }
};