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authorVincent Abriou <vincent.abriou@st.com>2015-06-04 13:59:02 +0200
committerBenjamin Gaignard <benjamin.gaignard@linaro.org>2015-06-08 15:28:28 +0200
commitc58d6d1b6652b0a8db4aef7e93fb21ee869b5387 (patch)
treed9b6092283181a07054e043eb978b8c1d89f89c9
parent8661532a6cf841fdab20d7e1868e6fd99a226d32 (diff)
downloadkernel-2015-06-08-st-drm-next.tar.gz
drm/sti: vtg fix CEA-861E video format timing error2015-06-08-st-drm-next
HDMI analyzer tests showed that Vsync and Hsync signal were not compliant with the HDMI protocol. HDMI_DELAY should be taken into account in the VTG Vsync programming to reflect the 6 pixels shift introduced in the VTG Hsync programming. Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
-rw-r--r--drivers/gpu/drm/sti/sti_vtg.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/sti/sti_vtg.c b/drivers/gpu/drm/sti/sti_vtg.c
index df855baffe74..aa8097137701 100644
--- a/drivers/gpu/drm/sti/sti_vtg.c
+++ b/drivers/gpu/drm/sti/sti_vtg.c
@@ -173,8 +173,11 @@ static void vtg_set_mode(struct sti_vtg *vtg,
tmp |= 1;
writel(tmp, vtg->regs + VTG_TOP_V_VD_1);
writel(tmp, vtg->regs + VTG_BOT_V_VD_1);
- writel(0, vtg->regs + VTG_TOP_V_HD_1);
- writel(0, vtg->regs + VTG_BOT_V_HD_1);
+
+ tmp = HDMI_DELAY << 16;
+ tmp |= HDMI_DELAY;
+ writel(tmp, vtg->regs + VTG_TOP_V_HD_1);
+ writel(tmp, vtg->regs + VTG_BOT_V_HD_1);
/* prepare VTG set 2 for for HD DCS */
tmp = (mode->hsync_end - mode->hsync_start) << 16;