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path: root/plat/socionext/synquacer/sq_helpers.S
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/*
 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <arch.h>
#include <asm_macros.S>
#include <assert_macros.S>
#include <platform_def.h>

	.global	sq_calc_core_pos
	.global	plat_my_core_pos
	.global	platform_mem_init
	.global	plat_is_my_cpu_primary
	.global plat_secondary_cold_boot_setup
	.global	plat_crash_console_init
	.global	plat_crash_console_putc
	.global	plat_crash_console_flush

/*
 * unsigned int sq_calc_core_pos(u_register_t mpidr)
 * core_pos = (cluster_id * max_cpus_per_cluster) + core_id
 */
func sq_calc_core_pos
	and	x1, x0, #MPIDR_CPU_MASK
	and	x0, x0, #MPIDR_CLUSTER_MASK
	add	x0, x1, x0, lsr #7
	ret
endfunc sq_calc_core_pos

func plat_my_core_pos
	mrs	x0, mpidr_el1
	b	sq_calc_core_pos
endfunc plat_my_core_pos

func platform_mem_init
	ret
endfunc platform_mem_init

/*
 * Secondary CPUs are placed in a holding pen, waiting for their mailbox
 * to be populated. Note that all CPUs share the same mailbox ; therefore,
 * populating it will release all CPUs from their holding pen. If
 * finer-grained control is needed then this should be handled in the
 * code that secondary CPUs jump to.
 */
func plat_secondary_cold_boot_setup
	ldr	x0, sq_sec_entrypoint

	/* Wait until the mailbox gets populated */
poll_mailbox:
	cbz	x0, 1f
	br	x0
1:
	wfe
	b	poll_mailbox
endfunc plat_secondary_cold_boot_setup

/*
 * Find out whether the current cpu is the primary
 * cpu (applicable only after a cold boot)
 */
func plat_is_my_cpu_primary
	mov	x9, x30
	bl	plat_my_core_pos
	ldr	x1, =SQ_BOOT_CFG_ADDR
	ldr	x1, [x1]
	ubfx	x1, x1, #PLAT_SQ_PRIMARY_CPU_SHIFT, \
			#PLAT_SQ_PRIMARY_CPU_BIT_WIDTH
	cmp	x0, x1
	cset	w0, eq
	ret	x9
endfunc plat_is_my_cpu_primary

/*
 * int plat_crash_console_init(void)
 * Function to initialize the crash console
 * without a C Runtime to print crash report.
 * Clobber list : x0, x1, x2
 */
func plat_crash_console_init
	mov_imm x0, PLAT_SQ_BOOT_UART_BASE
	mov_imm x1, PLAT_SQ_BOOT_UART_CLK_IN_HZ
	mov_imm x2, SQ_CONSOLE_BAUDRATE
	b	console_pl011_core_init
endfunc plat_crash_console_init

/*
 * int plat_crash_console_putc(int c)
 * Function to print a character on the crash
 * console without a C Runtime.
 * Clobber list : x1, x2
 */
func plat_crash_console_putc
	mov_imm	x1, PLAT_SQ_BOOT_UART_BASE
	b	console_pl011_core_putc
endfunc plat_crash_console_putc

/*
 * int plat_crash_console_flush(int c)
 * Function to force a write of all buffered
 * data that hasn't been output.
 * Out : return -1 on error else return 0.
 * Clobber list : x0, x1
 */
func plat_crash_console_flush
	mov_imm	x0, PLAT_SQ_BOOT_UART_BASE
	b	console_pl011_core_flush
endfunc plat_crash_console_flush

	/* -------------------------------------------------------------
	 * On the Socionext SynQuacer platform, we need to prevent the
	 * OS from using write combine mappings on PCIe MMIO regions.
	 * Let's do so by setting a stage 2 override for those regions,
	 * and run the OS in EL1 with stage 2 translations enabled.
	 * While we're at it, remap the config space of bus #0 on both
	 * RCs so we can use a generic ECAM driver.
	 * -------------------------------------------------------------
	 */

#define	VTCR_T0SZ	(64 - 40)
#define	VTCR_SL0	(1 << 6)	/* start at level 1 */
#define	VTCR_IRGN0	(3 << 8)	/* inner wbwa */
#define	VTCR_ORGN0	(3 << 10)	/* outer wbwa */
#define	VTCR_SH0	(0 << 12)	/* non shareable */
#define	VTCR_TG0	(0 << 14)	/* 4 KB granule */
#define	VTCR_PS		(2 << 16)	/* 40 bit PAs */
#define	VTCR_RES1	(1 << 31)	/* RES1 */

	.globl		bl31_setup_s2_translation
func bl31_setup_s2_translation
	mov_imm		x0, (PRELOADED_BL33_BASE - 0x8000)
	msr		vttbr_el2, x0
	mov_imm		x0, VTCR_T0SZ | VTCR_SL0 | VTCR_IRGN0 | \
			    VTCR_ORGN0 | VTCR_SH0 | VTCR_TG0 | \
			    VTCR_PS | VTCR_RES1
	msr		vtcr_el2, x0
	isb

	mrs		x0, hcr_el2
	orr		x0, x0, #1
	msr		hcr_el2, x0
	isb

	/*
	 * The so-called 'north SMMU' translates accesses to the slave ports of
	 * the PCIe blocks, and so it can be used to translate accesses to the
	 * PCIe config space. Older versions of the SCP firmware do not remap it
	 * in an ECAM compatible fashion  for the CPUs, (i.e., to work around
	 * limitations of the Synopsys IP) so let's do it here instead.
	 */
	mov_imm		x0, 0x4042800		// address and value of level 2
	mov_imm		x1, 0xC00060000445	// block entry for 0x6000_0000
	ldr		x2, [x0]
	cmp		x1, x2			// bail if the entry does not
	b.ne		0f			// have the expected value

	mov_imm		x1, (PRELOADED_BL33_BASE - 0x2000) | 3
	str		x1, [x0]		// 0x6000_0000 - 0x601f_ffff
	add		x1, x1, #0x1000
	str		x1, [x0, #0x400]	// 0x7000_0000 - 0x701f_ffff
	dmb		sy

0:	ret
endfunc bl31_setup_s2_translation