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authorshameer <shamiali2008@gmail.com>2017-05-20 19:45:10 +0100
committerGraeme Gregory <graeme.gregory@linaro.org>2017-06-06 10:00:44 +0100
commit37edf0f0978a06e825a1ef449183adf79d12deca (patch)
tree60fd3384814c8b615d90f44906834ebbd5e3b188 /fs/nfs/super.c
parent0d2d2a67c95fd4304dd00b935a6695131e9ab12b (diff)
downloadleg-kernel-37edf0f0978a06e825a1ef449183adf79d12deca.tar.gz
KVM:arm/arm64: HiSilicon GIC quirk for kvm CPU stall issue
KVM uses virt-phys interrupt map feature while forwarding the timer interrupt to Guest (ICH_LR HW bit=1). At present GIC on HiSilicon platforms(D02/D03) has issues with this feature and causes CPU stall. This patch uses non mapped timer irq inject into the Guest. When Guest deactivates the timer irq, a maintenance EOI irq is generated and KVM handles the deactivation on phys distributor. Signed-off-by: shameer <shamiali2008@gmail.com> Remove dts and change matching to HIP05/HIP06 Disable pr_warn("Unexpected interrupt %d on vcpu %p\n", irq, vcpu); There is a bug in D03 board that doesn't always clear interrupt, but this doesn't impact the functionality, so disable the warning. Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org>
Diffstat (limited to 'fs/nfs/super.c')
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