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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2020-01-23 13:45:23 +0200
committerTero Kristo <t-kristo@ti.com>2020-01-24 09:30:24 +0200
commit8c0deacaf40b523820419ac749cd955bfd66c6c7 (patch)
tree7d1f94cba0fa53db247cb9adaeb9e490e9d03c6d /arch/arm64
parent3d6230548c308c5fcb10f567ff44e6f23567f719 (diff)
downloadkernel-8c0deacaf40b523820419ac749cd955bfd66c6c7.tar.gz
arm64: dts: ti: k3-j721e: Correct the address for MAIN NAVSS
On am654 the MAIN NAVSS base address was 0x30800000, but in j721e it is at 0x30000000 Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/boot/dts/ti/k3-j721e.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index ee5470edb435..027bd1febafa 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -130,7 +130,7 @@
<0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
<0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
- <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
+ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
<0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */