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-rw-r--r--plat/fvp/drivers/pwrc/fvp_pwrc.c33
-rw-r--r--plat/fvp/include/plat_macros.S2
2 files changed, 15 insertions, 20 deletions
diff --git a/plat/fvp/drivers/pwrc/fvp_pwrc.c b/plat/fvp/drivers/pwrc/fvp_pwrc.c
index d1feece..c32c322 100644
--- a/plat/fvp/drivers/pwrc/fvp_pwrc.c
+++ b/plat/fvp/drivers/pwrc/fvp_pwrc.c
@@ -41,59 +41,54 @@ static bakery_lock_t pwrc_lock __attribute__ ((section("tzfw_coherent_mem")));
unsigned int fvp_pwrc_get_cpu_wkr(unsigned long mpidr)
{
- unsigned int rc = 0;
- bakery_lock_get(mpidr, &pwrc_lock);
- mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr);
- rc = PSYSR_WK(mmio_read_32(PWRC_BASE + PSYSR_OFF));
- bakery_lock_release(mpidr, &pwrc_lock);
- return rc;
+ return PSYSR_WK(fvp_pwrc_read_psysr(mpidr));
}
unsigned int fvp_pwrc_read_psysr(unsigned long mpidr)
{
- unsigned int rc = 0;
- bakery_lock_get(mpidr, &pwrc_lock);
+ unsigned int rc;
+ bakery_lock_get(&pwrc_lock);
mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr);
rc = mmio_read_32(PWRC_BASE + PSYSR_OFF);
- bakery_lock_release(mpidr, &pwrc_lock);
+ bakery_lock_release(&pwrc_lock);
return rc;
}
void fvp_pwrc_write_pponr(unsigned long mpidr)
{
- bakery_lock_get(mpidr, &pwrc_lock);
+ bakery_lock_get(&pwrc_lock);
mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr);
- bakery_lock_release(mpidr, &pwrc_lock);
+ bakery_lock_release(&pwrc_lock);
}
void fvp_pwrc_write_ppoffr(unsigned long mpidr)
{
- bakery_lock_get(mpidr, &pwrc_lock);
+ bakery_lock_get(&pwrc_lock);
mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr);
- bakery_lock_release(mpidr, &pwrc_lock);
+ bakery_lock_release(&pwrc_lock);
}
void fvp_pwrc_set_wen(unsigned long mpidr)
{
- bakery_lock_get(mpidr, &pwrc_lock);
+ bakery_lock_get(&pwrc_lock);
mmio_write_32(PWRC_BASE + PWKUPR_OFF,
(unsigned int) (PWKUPR_WEN | mpidr));
- bakery_lock_release(mpidr, &pwrc_lock);
+ bakery_lock_release(&pwrc_lock);
}
void fvp_pwrc_clr_wen(unsigned long mpidr)
{
- bakery_lock_get(mpidr, &pwrc_lock);
+ bakery_lock_get(&pwrc_lock);
mmio_write_32(PWRC_BASE + PWKUPR_OFF,
(unsigned int) mpidr);
- bakery_lock_release(mpidr, &pwrc_lock);
+ bakery_lock_release(&pwrc_lock);
}
void fvp_pwrc_write_pcoffr(unsigned long mpidr)
{
- bakery_lock_get(mpidr, &pwrc_lock);
+ bakery_lock_get(&pwrc_lock);
mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr);
- bakery_lock_release(mpidr, &pwrc_lock);
+ bakery_lock_release(&pwrc_lock);
}
/* Nothing else to do here apart from initializing the lock */
diff --git a/plat/fvp/include/plat_macros.S b/plat/fvp/include/plat_macros.S
index bdd402d..d2e7cbc 100644
--- a/plat/fvp/include/plat_macros.S
+++ b/plat/fvp/include/plat_macros.S
@@ -47,7 +47,7 @@ gic_regs: .asciz "gic_iar", "gic_ctlr", ""
bl fvp_get_cfgvar
/* gic base address is now in x0 */
ldr w1, [x0, #GICC_IAR]
- ldr w2, [x0, #GICD_CTLR]
+ ldr w2, [x0, #GICC_CTLR]
sub sp, sp, #GIC_REG_SIZE
stp x1, x2, [sp] /* we store the gic registers as 64 bit */
adr x0, gic_regs