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authordanh-arm <dan.handley@arm.com>2014-06-24 16:48:31 +0100
committerdanh-arm <dan.handley@arm.com>2014-06-24 16:48:31 +0100
commite73af8ac6849607281d5880d4c05798fe00b5d24 (patch)
tree84761275dfb8a07fc75bf0affea1d041697aa7ec /bl32/tsp
parent9d302ed22f6990cbb3f720bf42893b2a0d332b7d (diff)
parent4f2104ff20753d78af0058e3ca5e9e042cd707af (diff)
downloadarm-trusted-firmware-e73af8ac6849607281d5880d4c05798fe00b5d24.tar.gz
Merge pull request #152 from jcastillo-arm/jc/tf-issues/073-v2
Remove all checkpatch errors from codebase
Diffstat (limited to 'bl32/tsp')
-rw-r--r--bl32/tsp/tsp_interrupt.c4
-rw-r--r--bl32/tsp/tsp_timer.c10
2 files changed, 7 insertions, 7 deletions
diff --git a/bl32/tsp/tsp_interrupt.c b/bl32/tsp/tsp_interrupt.c
index 4a4b877..ff6bdc5 100644
--- a/bl32/tsp/tsp_interrupt.c
+++ b/bl32/tsp/tsp_interrupt.c
@@ -72,7 +72,7 @@ void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3)
* architecture version in v2.0 and the secure physical timer interrupt is the
* only S-EL1 interrupt that it needs to handle.
******************************************************************************/
-int32_t tsp_fiq_handler()
+int32_t tsp_fiq_handler(void)
{
uint64_t mpidr = read_mpidr();
uint32_t linear_id = platform_get_core_pos(mpidr), id;
@@ -109,7 +109,7 @@ int32_t tsp_fiq_handler()
return 0;
}
-int32_t tsp_irq_received()
+int32_t tsp_irq_received(void)
{
uint64_t mpidr = read_mpidr();
uint32_t linear_id = platform_get_core_pos(mpidr);
diff --git a/bl32/tsp/tsp_timer.c b/bl32/tsp/tsp_timer.c
index 366640f..a7fdfda 100644
--- a/bl32/tsp/tsp_timer.c
+++ b/bl32/tsp/tsp_timer.c
@@ -46,7 +46,7 @@ static timer_context_t pcpu_timer_context[PLATFORM_CORE_COUNT];
/*******************************************************************************
* This function initializes the generic timer to fire every 0.5 second
******************************************************************************/
-void tsp_generic_timer_start()
+void tsp_generic_timer_start(void)
{
uint64_t cval;
uint32_t ctl = 0;
@@ -63,7 +63,7 @@ void tsp_generic_timer_start()
/*******************************************************************************
* This function deasserts the timer interrupt and sets it up again
******************************************************************************/
-void tsp_generic_timer_handler()
+void tsp_generic_timer_handler(void)
{
/* Ensure that the timer did assert the interrupt */
assert(get_cntp_ctl_istatus(read_cntps_ctl_el1()));
@@ -76,7 +76,7 @@ void tsp_generic_timer_handler()
/*******************************************************************************
* This function deasserts the timer interrupt prior to cpu power down
******************************************************************************/
-void tsp_generic_timer_stop()
+void tsp_generic_timer_stop(void)
{
/* Disable the timer */
write_cntps_ctl_el1(0);
@@ -85,7 +85,7 @@ void tsp_generic_timer_stop()
/*******************************************************************************
* This function saves the timer context prior to cpu suspension
******************************************************************************/
-void tsp_generic_timer_save()
+void tsp_generic_timer_save(void)
{
uint32_t linear_id = platform_get_core_pos(read_mpidr());
@@ -98,7 +98,7 @@ void tsp_generic_timer_save()
/*******************************************************************************
* This function restores the timer context post cpu resummption
******************************************************************************/
-void tsp_generic_timer_restore()
+void tsp_generic_timer_restore(void)
{
uint32_t linear_id = platform_get_core_pos(read_mpidr());