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authorAchin Gupta <achin.gupta@arm.com>2014-02-09 13:30:38 +0000
committerDan Handley <dan.handley@arm.com>2014-02-20 19:06:34 +0000
commita0cd989dd589acaa6cddaa6617bd59dde0b8ce26 (patch)
tree024d969981366ae673f1dc4c56a3cd659e81ddd5 /bl31/bl31.ld.S
parent35ca35119d9dc51f1665184ab6db5e2861c213b4 (diff)
downloadarm-trusted-firmware-a0cd989dd589acaa6cddaa6617bd59dde0b8ce26.tar.gz
Factor out translation table setup in ARM FVP port
This patch factors out the ARM FVP specific code to create MMU translation tables so that it is possible for a boot loader stage to create a different set of tables instead of using the default ones. The default translation tables are created with the assumption that the calling boot loader stage executes out of secure SRAM. This might not be true for the BL3_2 stage in the future. A boot loader stage can define the `fill_xlation_tables()` function as per its requirements. It returns a reference to the level 1 translation table which is used by the common platform code to setup the TTBR_EL3. This patch is a temporary solution before a larger rework of translation table creation logic is introduced. Change-Id: I09a075d5da16822ee32a411a9dbe284718fb4ff6
Diffstat (limited to 'bl31/bl31.ld.S')
-rw-r--r--bl31/bl31.ld.S11
1 files changed, 10 insertions, 1 deletions
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index 859ccfe..7b42399 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -69,7 +69,7 @@ SECTIONS
} >RAM
/*
- * The .xlat_table section is for full, aligned page tables (4K).
+ * The xlat_table section is for full, aligned page tables (4K).
* Removing them from .bss avoids forcing 4K alignment on
* the .bss section and eliminates the unecessary zero init
*/
@@ -101,6 +101,15 @@ SECTIONS
} >RAM
/*
+ * The .xlat_table section is for full, aligned page tables (4K).
+ * Removing them from .bss avoids forcing 4K alignment on
+ * the .bss section and eliminates the unecessary zero init
+ */
+ xlat_table (NOLOAD) : {
+ *(xlat_table)
+ } >RAM
+
+ /*
* The base address of the coherent memory section must be page-aligned (4K)
* to guarantee that the coherent data are stored on their own pages and
* are not mixed with normal data. This is required to set up the correct