path: root/bl31/aarch64
diff options
authorSandrine Bailleux <sandrine.bailleux@arm.com>2014-03-31 11:25:18 +0100
committerSandrine Bailleux <sandrine.bailleux@arm.com>2014-04-08 15:22:56 +0100
commit9e86490f8f14f25c7583aaf37412114219f3eb8e (patch)
tree97f364c0c7d33077fccaa737b806617bc9fc491b /bl31/aarch64
parent65a9c0e96a9fe033936f40b7603e0ae267b97d96 (diff)
Define frequency of system counter in platform code
BL3-1 architecture setup code programs the system counter frequency into the CNTFRQ_EL0 register. This frequency is defined by the platform, though. This patch introduces a new platform hook that the architecture setup code can call to retrieve this information. In the ARM FVP port, this returns the first entry of the frequency modes table from the memory mapped generic timer. All system counter setup code has been removed from BL1 as some platforms may not have initialized the system counters at this stage. The platform specific settings done exclusively in BL1 have been moved to BL3-1. In the ARM FVP port, this consists in enabling and initializing the System level generic timer. Also, the frequency change request in the counter control register has been set to 0 to make it explicit it's using the base frequency. The CNTCR_FCREQ() macro has been fixed in this context to give an entry number rather than a bitmask. In future, when support for firmware update is implemented, there is a case where BL1 platform specific code will need to program the counter frequency. This should be implemented at that time. This patch also updates the relevant documentation. It properly fixes ARM-software/tf-issues#24 Change-Id: If95639b279f75d66ac0576c48a6614b5ccb0e84b
Diffstat (limited to 'bl31/aarch64')
1 files changed, 3 insertions, 8 deletions
diff --git a/bl31/aarch64/bl31_arch_setup.c b/bl31/aarch64/bl31_arch_setup.c
index faca2a1..793b895 100644
--- a/bl31/aarch64/bl31_arch_setup.c
+++ b/bl31/aarch64/bl31_arch_setup.c
@@ -40,7 +40,7 @@
void bl31_arch_setup(void)
unsigned long tmp_reg = 0;
- unsigned int counter_base_frequency;
+ uint64_t counter_freq;
/* Enable alignment checks and set the exception endianness to LE */
tmp_reg = read_sctlr_el3();
@@ -62,14 +62,9 @@ void bl31_arch_setup(void)
- /* Read the frequency from Frequency modes table */
- counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
- /* The first entry of the frequency modes table must not be 0 */
- assert(counter_base_frequency != 0);
/* Program the counter frequency */
- write_cntfrq_el0(counter_base_frequency);
- return;
+ counter_freq = plat_get_syscnt_freq();
+ write_cntfrq_el0(counter_freq);