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authorSandrine Bailleux <sandrine.bailleux@arm.com>2014-03-31 10:44:09 +0100
committerSandrine Bailleux <sandrine.bailleux@arm.com>2014-04-08 15:22:56 +0100
commit65a9c0e96a9fe033936f40b7603e0ae267b97d96 (patch)
tree2317b487f3fd5895d0af80a354a3365150904c47 /bl31/aarch64
parente6e54a18f80318e2fcf98f4f8810705618cdea79 (diff)
downloadarm-trusted-firmware-65a9c0e96a9fe033936f40b7603e0ae267b97d96.tar.gz
Revert "Move architecture timer setup to platform-specific code"
This reverts commit 1c297bf015226c182b66498d5a64b8b51c7624f5 because it introduced a bug: the CNTFRQ_EL0 register was no longer programmed by all CPUs. bl31_platform_setup() function is invoked only in the cold boot path and consequently only on the primary cpu. A subsequent commit will correctly implement the necessary changes to the counter frequency setup code. Fixes ARM-software/tf-issues#125 Conflicts: docs/firmware-design.md plat/fvp/bl31_plat_setup.c Change-Id: Ib584ad7ed069707ac04cf86717f836136ad3ab54
Diffstat (limited to 'bl31/aarch64')
-rw-r--r--bl31/aarch64/bl31_arch_setup.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/bl31/aarch64/bl31_arch_setup.c b/bl31/aarch64/bl31_arch_setup.c
index 2a424f8..faca2a1 100644
--- a/bl31/aarch64/bl31_arch_setup.c
+++ b/bl31/aarch64/bl31_arch_setup.c
@@ -40,6 +40,7 @@
void bl31_arch_setup(void)
{
unsigned long tmp_reg = 0;
+ unsigned int counter_base_frequency;
/* Enable alignment checks and set the exception endianness to LE */
tmp_reg = read_sctlr_el3();
@@ -61,6 +62,13 @@ void bl31_arch_setup(void)
enable_serror();
enable_debug_exceptions();
+ /* Read the frequency from Frequency modes table */
+ counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
+ /* The first entry of the frequency modes table must not be 0 */
+ assert(counter_base_frequency != 0);
+
+ /* Program the counter frequency */
+ write_cntfrq_el0(counter_base_frequency);
return;
}