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authorSandrine Bailleux <sandrine.bailleux@arm.com>2013-11-18 17:26:59 +0000
committerDan Handley <dan.handley@arm.com>2013-11-27 15:31:06 +0000
commit3738274dc1b40ad846d41d7bfd6a597bcfba9e70 (patch)
tree136c4d81d7b4f285ee37f1fdf674df5332a238d4 /bl31/aarch64
parent204aa03da7d8a34d5e06fba3ccc9e565ed01d305 (diff)
downloadarm-trusted-firmware-3738274dc1b40ad846d41d7bfd6a597bcfba9e70.tar.gz
Unmask SError and Debug exceptions.
Any asynchronous exception caused by the firmware should be handled in the firmware itself. For this reason, unmask SError exceptions (and Debug ones as well) on all boot paths. Also route external abort and SError interrupts to EL3, otherwise they will target EL1. Change-Id: I9c191d2d0dcfef85f265641c8460dfbb4d112092
Diffstat (limited to 'bl31/aarch64')
-rw-r--r--bl31/aarch64/bl31_arch_setup.c13
1 files changed, 10 insertions, 3 deletions
diff --git a/bl31/aarch64/bl31_arch_setup.c b/bl31/aarch64/bl31_arch_setup.c
index f6fa088..238af7b 100644
--- a/bl31/aarch64/bl31_arch_setup.c
+++ b/bl31/aarch64/bl31_arch_setup.c
@@ -49,12 +49,19 @@ void bl31_arch_setup(void)
write_sctlr(tmp_reg);
/*
- * Enable HVCs, allow NS to mask CPSR.A, route FIQs to EL3, set the
- * next EL to be aarch64
+ * Enable HVCs, route FIQs to EL3, set the next EL to be AArch64, route
+ * external abort and SError interrupts to EL3
*/
- tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_HCE_BIT | SCR_FIQ_BIT;
+ tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_HCE_BIT | SCR_EA_BIT |
+ SCR_FIQ_BIT;
write_scr(tmp_reg);
+ /*
+ * Enable SError and Debug exceptions
+ */
+ enable_serror();
+ enable_debug_exceptions();
+
/* Do not trap coprocessor accesses from lower ELs to EL3 */
write_cptr_el3(0);