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authorAndrew Thoelke <andrew.thoelke@arm.com>2014-03-20 10:48:23 +0000
committerAndrew Thoelke <andrew.thoelke@arm.com>2014-04-15 15:49:29 +0100
commit2bf28e620a6f05700753a2b45a888c6623e20723 (patch)
treec35374e36508ddf0c10324e9b511c983655213e4 /bl31/aarch64
parent9c2c763d22469b0f73d76469442b474c08497e7a (diff)
downloadarm-trusted-firmware-2bf28e620a6f05700753a2b45a888c6623e20723.tar.gz
Allocate single stacks for BL1 and BL2
The BL images share common stack management code which provides one coherent and one cacheable stack for every CPU. BL1 and BL2 just execute on the primary CPU during boot and do not require the additional CPU stacks. This patch provides separate stack support code for UP and MP images, substantially reducing the RAM usage for BL1 and BL2 for the FVP platform. This patch also provides macros for declaring stacks and calculating stack base addresses to improve consistency where this has to be done in the firmware. The stack allocation source files are now included via platform.mk rather than the common BLx makefiles. This allows each platform to select the appropriate MP/UP stack support for each BL image. Each platform makefile must be updated when including this commit. Fixes ARM-software/tf-issues#76 Change-Id: Ia251f61b8148ffa73eae3f3711f57b1ffebfa632
Diffstat (limited to 'bl31/aarch64')
-rw-r--r--bl31/aarch64/runtime_exceptions.S15
1 files changed, 3 insertions, 12 deletions
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index e16d8d9..d00c1d7 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -435,21 +435,12 @@ restore_scratch_registers_callee:
*/
func get_exception_stack
mov x10, x30 // lr
- bl platform_get_core_pos
- add x0, x0, #1
- mov x1, #PCPU_EXCEPTION_STACK_SIZE
- mul x0, x0, x1
- ldr x1, =pcpu_exception_stack
- add x0, x1, x0
+ get_mp_stack pcpu_exception_stack, PCPU_EXCEPTION_STACK_SIZE
ret x10
/* -----------------------------------------------------
* Per-cpu exception stacks in normal memory.
* -----------------------------------------------------
*/
- .section tzfw_normal_stacks, "aw", %nobits; .align 6
-
-pcpu_exception_stack:
- /* Zero fill */
- .space (PLATFORM_CORE_COUNT * PCPU_EXCEPTION_STACK_SIZE), 0
-
+declare_stack pcpu_exception_stack, tzfw_normal_stacks, \
+ PCPU_EXCEPTION_STACK_SIZE, PLATFORM_CORE_COUNT