path: root/bl31/aarch64
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authorJeenu Viswambharan <jeenu.viswambharan@arm.com>2014-01-07 10:21:18 +0000
committerDan Handley <dan.handley@arm.com>2014-03-10 14:17:59 +0000
commit1c297bf015226c182b66498d5a64b8b51c7624f5 (patch)
tree599f1d5a6bec18bc5ce9f9964c0c4a0b6f0955eb /bl31/aarch64
parent92a12866e6ab01c284f7aff01818c65851880bfd (diff)
Move architecture timer setup to platform-specific code
At present, bl1_arch_setup() and bl31_arch_setup() program the counter frequency using a value from the memory mapped generic timer. The generic timer however is not necessarily present on all ARM systems (although it is architected to be present on all server systems). This patch moves the timer setup to platform-specific code and updates the relevant documentation. Also, CNTR.FCREQ is set as the specification requires the bit corresponding to the counter's frequency to be set when enabling. Since we intend to use the base frequency, set bit 8. Fixes ARM-software/tf-issues#24 Change-Id: I32c52cf882253e01f49056f47c58c23e6f422652
Diffstat (limited to 'bl31/aarch64')
1 files changed, 0 insertions, 8 deletions
diff --git a/bl31/aarch64/bl31_arch_setup.c b/bl31/aarch64/bl31_arch_setup.c
index 03b9623..faeccf3 100644
--- a/bl31/aarch64/bl31_arch_setup.c
+++ b/bl31/aarch64/bl31_arch_setup.c
@@ -40,7 +40,6 @@
void bl31_arch_setup(void)
unsigned long tmp_reg = 0;
- unsigned int counter_base_frequency;
/* Enable alignment checks and set the exception endianness to LE */
tmp_reg = read_sctlr();
@@ -62,13 +61,6 @@ void bl31_arch_setup(void)
- /* Read the frequency from Frequency modes table */
- counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
- /* The first entry of the frequency modes table must not be 0 */
- assert(counter_base_frequency != 0);
- /* Program the counter frequency */
- write_cntfrq_el0(counter_base_frequency);