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authorAndrew Thoelke <andrew.thoelke@arm.com>2014-06-04 21:10:52 +0100
committerAndrew Thoelke <andrew.thoelke@arm.com>2014-06-23 14:55:44 +0100
commit167a935733a6e3e412b8ed6a60034d0d84895f2e (patch)
treec443557e8fe8ff50628567aa6ebfc11f6fc9f6dd /bl31/aarch64
parent5298f2cb98b9bdc18eb2f25cd28180ba7fd000d8 (diff)
downloadarm-trusted-firmware-167a935733a6e3e412b8ed6a60034d0d84895f2e.tar.gz
Initialise CPU contexts from entry_point_info
Consolidate all BL3-1 CPU context initialization for cold boot, PSCI and SPDs into two functions: * The first uses entry_point_info to initialize the relevant cpu_context for first entry into a lower exception level on a CPU * The second populates the EL1 and EL2 system registers as needed from the cpu_context to ensure correct entry into the lower EL This patch alters the way that BL3-1 determines which exception level is used when first entering EL1 or EL2 during cold boot - this is now fully determined by the SPSR value in the entry_point_info for BL3-3, as set up by the platform code in BL2 (or otherwise provided to BL3-1). In the situation that EL1 (or svc mode) is selected for a processor that supports EL2, the context management code will now configure all essential EL2 register state to ensure correct execution of EL1. This allows the platform code to run non-secure EL1 payloads directly without requiring a small EL2 stub or OS loader. Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f
Diffstat (limited to 'bl31/aarch64')
-rw-r--r--bl31/aarch64/bl31_arch_setup.c44
-rw-r--r--bl31/aarch64/context.S6
2 files changed, 6 insertions, 44 deletions
diff --git a/bl31/aarch64/bl31_arch_setup.c b/bl31/aarch64/bl31_arch_setup.c
index ad73de0..e0382b3 100644
--- a/bl31/aarch64/bl31_arch_setup.c
+++ b/bl31/aarch64/bl31_arch_setup.c
@@ -51,11 +51,11 @@ void bl31_arch_setup(void)
write_sctlr_el3(tmp_reg);
/*
- * Enable HVCs, route FIQs to EL3, set the next EL to be AArch64, route
- * external abort and SError interrupts to EL3
+ * Route external abort and SError interrupts to EL3
+ * other SCR bits will be configured before exiting to a lower exception
+ * level
*/
- tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_HCE_BIT | SCR_EA_BIT |
- SCR_FIQ_BIT;
+ tmp_reg = SCR_RES1_BITS | SCR_EA_BIT;
write_scr(tmp_reg);
/*
@@ -68,39 +68,3 @@ void bl31_arch_setup(void)
counter_freq = plat_get_syscnt_freq();
write_cntfrq_el0(counter_freq);
}
-
-/*******************************************************************************
- * Detect what the security state of the next EL is and setup the minimum
- * required architectural state: program SCTRL to reflect the RES1 bits, and to
- * have MMU and caches disabled
- ******************************************************************************/
-void bl31_next_el_arch_setup(uint32_t security_state)
-{
- unsigned long id_aa64pfr0 = read_id_aa64pfr0_el1();
- unsigned long next_sctlr;
- unsigned long el_status;
- unsigned long scr = read_scr();
-
- /* Use the same endianness than the current BL */
- next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT);
-
- /* Find out which EL we are going to */
- el_status = (id_aa64pfr0 >> ID_AA64PFR0_EL2_SHIFT) & ID_AA64PFR0_ELX_MASK;
-
- if (security_state == NON_SECURE) {
- /* Check if EL2 is supported */
- if (el_status && (scr & SCR_HCE_BIT)) {
- /* Set SCTLR EL2 */
- next_sctlr |= SCTLR_EL2_RES1;
- write_sctlr_el2(next_sctlr);
- return;
- }
- }
-
- /*
- * SCTLR_EL1 needs the same programming irrespective of the
- * security state of EL1.
- */
- next_sctlr |= SCTLR_EL1_RES1;
- write_sctlr_el1(next_sctlr);
-}
diff --git a/bl31/aarch64/context.S b/bl31/aarch64/context.S
index d0bca64..6667419 100644
--- a/bl31/aarch64/context.S
+++ b/bl31/aarch64/context.S
@@ -43,9 +43,8 @@
.global el3_sysregs_context_save
func el3_sysregs_context_save
- mrs x9, scr_el3
mrs x10, sctlr_el3
- stp x9, x10, [x0, #CTX_SCR_EL3]
+ str x10, [x0, #CTX_SCTLR_EL3]
mrs x11, cptr_el3
stp x11, xzr, [x0, #CTX_CPTR_EL3]
@@ -98,8 +97,7 @@ func el3_sysregs_context_restore
/* Make sure all the above changes are observed */
isb
- ldp x9, x10, [x0, #CTX_SCR_EL3]
- msr scr_el3, x9
+ ldr x10, [x0, #CTX_SCTLR_EL3]
msr sctlr_el3, x10
isb