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authordanh-arm <dan.handley@arm.com>2014-06-18 18:34:31 +0100
committerdanh-arm <dan.handley@arm.com>2014-06-18 18:34:31 +0100
commite869310f67344cd1f2b531cff38fa8cb4d319d58 (patch)
treeb2cf966f62c8097e4498046c32ad55b3f209cbc8
parent5d292ab6fde45c5d7077c8a61cb339a0a9f69281 (diff)
parentb1e71b20d8061abff4496a8ce81d121bac1c3b10 (diff)
downloadarm-trusted-firmware-e869310f67344cd1f2b531cff38fa8cb4d319d58.tar.gz
Merge pull request #135 from soby-mathew/sm/remove-reinit-of-timers
Remove re-initialisation of system timers after warm boot for FVP
-rw-r--r--plat/fvp/fvp_pm.c13
1 files changed, 1 insertions, 12 deletions
diff --git a/plat/fvp/fvp_pm.c b/plat/fvp/fvp_pm.c
index d702643..03f06e7 100644
--- a/plat/fvp/fvp_pm.c
+++ b/plat/fvp/fvp_pm.c
@@ -290,7 +290,7 @@ int fvp_affinst_on_finish(unsigned long mpidr,
int rc = PSCI_E_SUCCESS;
unsigned long linear_id, cpu_setup;
mailbox_t *fvp_mboxes;
- unsigned int gicd_base, gicc_base, reg_val, ectlr;
+ unsigned int gicd_base, gicc_base, ectlr;
switch (afflvl) {
@@ -354,17 +354,6 @@ int fvp_affinst_on_finish(unsigned long mpidr,
/* TODO: This setup is needed only after a cold boot */
gic_pcpu_distif_setup(gicd_base);
- /* Allow access to the System counter timer module */
- reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
- reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
- reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
- mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val);
- mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
-
- reg_val = (1 << CNTNSAR_NS_SHIFT(0)) |
- (1 << CNTNSAR_NS_SHIFT(1));
- mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val);
-
break;
default: