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authorJeenu Viswambharan <jeenu.viswambharan@arm.com>2014-02-17 17:26:51 +0000
committerDan Handley <dan.handley@arm.com>2014-02-17 18:51:44 +0000
commit74cbb839838d770064f0c83010609a134b22f2f8 (patch)
treefab493fc7e626ae595ccf18a538b7bb3975bf227
parentd265bd7c3156178cd3c519ce923b491e3f188790 (diff)
downloadarm-trusted-firmware-74cbb839838d770064f0c83010609a134b22f2f8.tar.gz
Move translation tables into separate section
This patch moves the translation tables into their own section. This saves space that would otherwise have been lost in padding due to page table alignment constraints. The BL31 and BL32 bases have been consequently adjusted. Change-Id: Ibd65ae8a5ce4c4ea9a71a794c95bbff40dc63e65
-rw-r--r--bl1/bl1.ld.S9
-rw-r--r--bl2/bl2.ld.S9
-rw-r--r--bl31/bl31.ld.S9
-rw-r--r--plat/fvp/aarch64/plat_common.c4
-rw-r--r--plat/fvp/platform.h4
5 files changed, 31 insertions, 4 deletions
diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S
index 48828e8..969b8c2 100644
--- a/bl1/bl1.ld.S
+++ b/bl1/bl1.ld.S
@@ -77,6 +77,15 @@ SECTIONS
} >RAM
/*
+ * The .xlat_table section is for full, aligned page tables (4K).
+ * Removing them from .bss avoids forcing 4K alignment on
+ * the .bss section and eliminates the unecessary zero init
+ */
+ xlat_table (NOLOAD) : {
+ *(xlat_table)
+ } >RAM
+
+ /*
* The base address of the coherent memory section must be page-aligned (4K)
* to guarantee that the coherent data are stored on their own pages and
* are not mixed with normal data. This is required to set up the correct
diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S
index c1d5d5c..849297a 100644
--- a/bl2/bl2.ld.S
+++ b/bl2/bl2.ld.S
@@ -59,6 +59,15 @@ SECTIONS
__RO_END__ = .;
} >RAM
+ /*
+ * The .xlat_table section is for full, aligned page tables (4K).
+ * Removing them from .bss avoids forcing 4K alignment on
+ * the .bss section and eliminates the unecessary zero init
+ */
+ xlat_table (NOLOAD) : {
+ *(xlat_table)
+ } >RAM
+
.data . : {
__DATA_START__ = .;
*(.data)
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index 4232560..7cc8527 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -60,6 +60,15 @@ SECTIONS
__RO_END__ = .;
} >RAM
+ /*
+ * The .xlat_table section is for full, aligned page tables (4K).
+ * Removing them from .bss avoids forcing 4K alignment on
+ * the .bss section and eliminates the unecessary zero init
+ */
+ xlat_table (NOLOAD) : {
+ *(xlat_table)
+ } >RAM
+
.data . : {
__DATA_START__ = .;
*(.data)
diff --git a/plat/fvp/aarch64/plat_common.c b/plat/fvp/aarch64/plat_common.c
index 5b53aaf..c8c36d7 100644
--- a/plat/fvp/aarch64/plat_common.c
+++ b/plat/fvp/aarch64/plat_common.c
@@ -67,14 +67,14 @@ __attribute__ ((aligned((ADDR_SPACE_SIZE >> 30) << 3)));
* space needed to address secure peripherals e.g. trusted ROM and RAM.
******************************************************************************/
static unsigned long l2_xlation_table[NUM_L2_PAGETABLES][NUM_2MB_IN_GB]
-__attribute__ ((aligned(NUM_2MB_IN_GB << 3)));
+__attribute__ ((aligned(NUM_2MB_IN_GB << 3), section("xlat_table")));
/*******************************************************************************
* Level 3 translation tables (2 sets) describe the trusted & non-trusted RAM
* regions at a granularity of 4K.
******************************************************************************/
static unsigned long l3_xlation_table[NUM_L3_PAGETABLES][NUM_4K_IN_2MB]
-__attribute__ ((aligned(NUM_4K_IN_2MB << 3)));
+__attribute__ ((aligned(NUM_4K_IN_2MB << 3), section("xlat_table")));
/*******************************************************************************
* Helper to create a level 1/2 table descriptor which points to a level 2/3
diff --git a/plat/fvp/platform.h b/plat/fvp/platform.h
index a12a094..5826d35 100644
--- a/plat/fvp/platform.h
+++ b/plat/fvp/platform.h
@@ -225,12 +225,12 @@
/*******************************************************************************
* BL2 specific defines.
******************************************************************************/
-#define BL2_BASE 0x0402B000
+#define BL2_BASE 0x0402D000
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
-#define BL31_BASE 0x0400E000
+#define BL31_BASE 0x0400C000
/*******************************************************************************
* Platform specific page table and MMU setup constants