summaryrefslogtreecommitdiff
path: root/big-little/switcher/context/ns_context.c
blob: 254131989fcca4be05afd1bf89b7744407c2a4b4 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
/*
 * Copyright (c) 2012, ARM Limited. All rights reserved.
 *       
 * Redistribution and use in source and binary forms, with
 * or without modification, are permitted provided that the
 * following conditions are met:
 *     
 * Redistributions of source code must retain the above
 * copyright notice, this list of conditions and the 
 * following disclaimer.
 *
 * Redistributions in binary form must reproduce the
 * above copyright notice, this list of conditions and 
 * the following disclaimer in the documentation 
 * and/or other materials provided with the distribution.
 *      
 * Neither the name of ARM nor the names of its
 * contributors may be used to endorse or promote products
 * derived from this software without specific prior written
 * permission.                        
 */

#include "virt_helpers.h"
#include "vgiclib.h"
#include "gic_registers.h"
#include "int_master.h"
#include "context.h"
#include "bl.h"
#include "misc.h"
#include "events.h"
#include "virtualisor.h"
#include "helpers.h"

extern void gic_enable_int(unsigned);
extern void SetupVGIC(unsigned);
extern unsigned async_switchover;
extern unsigned hyp_timer_trigger;

/* Bakery locks to serialize access to the tube. */
static bakery_t lock_tube0 __attribute__ ((section("BL_DV_PAGE"))) = {
0};

static bakery_t lock_tube1 __attribute__ ((section("BL_DV_PAGE"))) = {
0};

/*
 * Top level structure which encapsulates the context of the entire
 * Kingfisher system
 */
system_context switcher_context = { 0 };

void stop_generic_timer(generic_timer_context * ctr_ctx)
{
	/*
	 * Disable the timer and mask the irq to prevent
	 * suprious interrupts on this cpu interface. It
	 * will bite us when we come back if we don't. It
	 * will be replayed on the inbound cluster.
	 */
	write_cntp_ctl(TIMER_MASK_IRQ);

	/* 
	 * If the local timer interrupt was being used as
	 * the asynchronous trigger, then it was disabled
	 * in handle_interrupt() to prevent this level-
	 * triggerred interrupt from firing. Now that its
	 * been acked at the peripheral. We can renable it
	 */
	if (!hyp_timer_trigger) {
		if (ctr_ctx->cntp_ctl & TIMER_IRQ_STAT)
			gic_enable_int(LCL_TIMER_IRQ);
	}

	return;
}

void save_context(unsigned first_cpu)
{
	unsigned cpu_id = read_cpuid();
	unsigned cluster_id = read_clusterid();
	cpu_context *ns_cpu_ctx =
	    &switcher_context.cluster.core[cpu_id].ns_cpu_ctx;
	unsigned *pmon_context = ns_cpu_ctx->pmon_regs;
	unsigned *gp_context = ns_cpu_ctx->banked_cpu_regs;
	unsigned *vfp_context = ns_cpu_ctx->vfp_regs;
	banked_cp15_context *cp15_context = &ns_cpu_ctx->banked_cp15_regs;
	gic_cpu_context *gic_pvt_context = &ns_cpu_ctx->gic_cpu_ctx;
	generic_timer_context *cp15_timer_ctx = &ns_cpu_ctx->cp15_timer_ctx;
	cp15_fault_regs *fault_ctx = &cp15_context->ns_cp15_fault_regs;

	write_trace(&lock_tube0, NS_TUBE0, "Context Save Start", read_cntpct(),
		    0x0, 0x0);

	/*
	 * Good place to bring the inbound cluster out of reset, but first
	 * we need to save the secure world context.
	 */
	write_trace(&lock_tube0, NS_TUBE0, "Secure Context Save Start",
		    read_cntpct(), 0x0, 0x0);
	smc(SMC_SEC_SAVE, (unsigned)hyp_warm_reset_handler);
	write_trace(&lock_tube0, NS_TUBE0, "Secure Context Save End",
		    read_cntpct(), 0x0, 0x0);

	/* 
	 * Save the 32-bit Generic timer context & stop them
	 */
	save_generic_timer((unsigned *)cp15_timer_ctx, 0x1);
	stop_generic_timer(cp15_timer_ctx);

	/* 
	 * Save v7 generic performance monitors 
	 * Save cpu general purpose banked registers
	 * Save cp15 context 
	 */
	save_performance_monitors(pmon_context);
	save_banked_registers(gp_context);
	save_cp15(cp15_context->cp15_misc_regs);
	save_control_registers(cp15_context->cp15_ctrl_regs, 0x0);
	save_mmu(cp15_context->cp15_mmu_regs);
	save_fault_status((unsigned *)fault_ctx);

	/*
	 * Check if non-secure world has access to the vfp/neon registers
	 * and save them if so.
	 */
	if (read_nsacr() & (0x3 << 10))
		save_vfp(vfp_context);

	/*
	 * Disable the GIC CPU interface tp prevent interrupts from waking
	 * the core from wfi() subsequently.
	 */
	write32(GIC_IC_PHY_BASE + GICC_CTL, 0x0);

	/* Save vGIC virtual cpu interface (cpu view) context */
	save_gic_interface(gic_pvt_context->gic_cpu_if_regs, VGIC_VM_PHY_BASE);

	/*
	 * Save the HYP view registers. These registers contain a snapshot
	 * of all the physical interrupts acknowledged till we 
	 * entered this HYP mode.
	 */
	vgic_savestate(cpu_id);

	/*
	 * TODO: 
	 * Is it safe for the secondary cpu to save its context
	 * while the GIC distributor is on. Should be as its
	 * banked context and the cpu itself is the only one
	 * who can change it. Still have to consider cases e.g
	 * SGIs/Localtimers becoming pending.
	 */
	save_gic_distributor_private(gic_pvt_context->gic_dist_if_pvt_regs,
				     GIC_ID_PHY_BASE);

	/* Safe place to save the Virtualisor context */
	SaveVirtualisor(first_cpu);

	/*
	 * Indicate to the inbound side that the context has been saved and is ready
	 * for pickup.
	 */
	write_trace(&lock_tube0, NS_TUBE0, "Context Save End", read_cntpct(),
		    0x0, 0x0);
	set_event(OB_CONTEXT_DONE, cpu_id);

	/*
	 * Now, we wait for the inbound cluster to signal that its done atleast picking 
	 * up the saved context.
	 */
	if (cpu_id == first_cpu) {
		wait_for_events(IB_CONTEXT_DONE);
		write_trace(&lock_tube0, NS_TUBE0, "Inbound done",
			    read_cntpct(), 0x0, 0x0);
	}

	return;
}

void restore_context(unsigned first_cpu)
{
	unsigned cpu_id = read_cpuid();
	unsigned cluster_id = read_clusterid();
	unsigned warm_reset = 1;
	cpu_context *ns_cpu_ctx =
	    &switcher_context.cluster.core[cpu_id].ns_cpu_ctx;
	global_context *gbl_context = &switcher_context.cluster.ns_cluster_ctx;
	unsigned *pmon_context = ns_cpu_ctx->pmon_regs;
	unsigned *gp_context = ns_cpu_ctx->banked_cpu_regs;
	unsigned *vfp_context = ns_cpu_ctx->vfp_regs;
	gic_cpu_context *gic_pvt_context = &ns_cpu_ctx->gic_cpu_ctx;
	generic_timer_context *cp15_timer_ctx = &ns_cpu_ctx->cp15_timer_ctx;
	banked_cp15_context *cp15_context = &ns_cpu_ctx->banked_cp15_regs;
	cp15_fault_regs *fault_ctx = &cp15_context->ns_cp15_fault_regs;
	vm_context *src = 0x0;
	vm_context *dest = 0x0;
	unsigned dest_cpuif = 0x0;
	unsigned src_cpuif = 0x0;

	/*
	 * Map cpuids to cpu interface numbers so that cpu interface
	 * specific context can be correctly restored on the external
	 * vGIC.
	 */
	map_cpuif(cluster_id, cpu_id);
	SetupVGIC(warm_reset);

	/*
	 * Inbound headstart i.e. the vGIC configuration, secure context
	 * restore & cache invalidation has been done. Now wait for the 
	 * outbound to provide the context.
	 */
	write_trace(&lock_tube1, NS_TUBE1, "Wait for context", read_cntpct(),
		    0x0, 0x0);
	wait_for_event(OB_CONTEXT_DONE, cpu_id);
	reset_event(OB_CONTEXT_DONE, cpu_id);

	/*
	 * First cpu restores the global context while the others take 
	 * care of their own.
	 */
	write_trace(&lock_tube1, NS_TUBE1, "Context Restore Start ",
		    read_cntpct(), 0x0, 0x0);
	if (cpu_id == first_cpu)
		restore_gic_distributor_shared(gbl_context->gic_dist_if_regs,
					       GIC_ID_PHY_BASE);
	restore_gic_distributor_private(gic_pvt_context->gic_dist_if_pvt_regs,
					GIC_ID_PHY_BASE);
	vgic_loadstate(cpu_id);

	SetupVirtualisor(first_cpu);

	/* Restore NS VGIC context */
	restore_gic_interface(gic_pvt_context->gic_cpu_if_regs,
			      VGIC_VM_PHY_BASE);

	/*
	 * Check if non-secure world has access to the vfp/neon registers
	 * and save them if so.
	 */
	if (read_nsacr() & (0x3 << 10))
		restore_vfp(vfp_context);

	/* 
	 * Restore cp15 context
	 * Restore cpu general purpose banked registers
	 * Restore v7 generic performance monitors 
	 * Restore the 32-bit Generic timer context
	 */
	restore_fault_status((unsigned *)fault_ctx);
	restore_mmu(cp15_context->cp15_mmu_regs);
	restore_control_registers(cp15_context->cp15_ctrl_regs, 0x0);
	restore_cp15(cp15_context->cp15_misc_regs);
	restore_banked_registers(gp_context);
	restore_performance_monitors(pmon_context);
	restore_generic_timer((unsigned *)cp15_timer_ctx, 0x1);

	/*
	 * Paranoid check to ensure that all HYP/Secure context & Virtualisor 
	 * is restored before any core enters the non-secure mode to use it.
	 */
	if (cpu_id == first_cpu) {
		set_events(HYP_CONTEXT_DONE);
	}
	wait_for_event(HYP_CONTEXT_DONE, cpu_id);
	reset_event(HYP_CONTEXT_DONE, cpu_id);

	/*
	 * Return the saved general purpose registers saved above the HYP mode   
	 * stack of our counterpart cpu on the other cluster.
	 */
	dest_cpuif = get_cpuif(cluster_id, cpu_id);
	src_cpuif = get_cpuif(!cluster_id, cpu_id);
	dest = &guestos_state[dest_cpuif].context;
	src = &guestos_state[src_cpuif].context;

	dest->gp_regs[0] = src->gp_regs[0];
	dest->gp_regs[1] = src->gp_regs[1];
	dest->gp_regs[2] = src->gp_regs[2];
	dest->gp_regs[3] = src->gp_regs[3];
	dest->gp_regs[4] = src->gp_regs[4];
	dest->gp_regs[5] = src->gp_regs[5];
	dest->gp_regs[6] = src->gp_regs[6];
	dest->gp_regs[7] = src->gp_regs[7];
	dest->gp_regs[8] = src->gp_regs[8];
	dest->gp_regs[9] = src->gp_regs[9];
	dest->gp_regs[10] = src->gp_regs[10];
	dest->gp_regs[11] = src->gp_regs[11];
	dest->gp_regs[12] = src->gp_regs[12];
	dest->gp_regs[13] = src->gp_regs[13];
	dest->gp_regs[14] = src->gp_regs[14];
	dest->elr_hyp = src->elr_hyp;
	dest->spsr = src->spsr;
	dest->usr_lr = src->usr_lr;

	write_trace(&lock_tube1, NS_TUBE1, "Context Restore End", read_cntpct(),
		    0x0, 0x0);
	set_event(IB_CONTEXT_DONE, cpu_id);

	if (async_switchover && cpu_id == first_cpu)
		enable_trigger(read_cntfrq());

	return;
}