summaryrefslogtreecommitdiff
path: root/big-little/common/vgic_setup.c
blob: 8c839ebfd2010333941f959f5a2f6779ff425d15 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
/*
 * Copyright (c) 2012, ARM Limited. All rights reserved.
 *       
 * Redistribution and use in source and binary forms, with
 * or without modification, are permitted provided that the
 * following conditions are met:
 *     
 * Redistributions of source code must retain the above
 * copyright notice, this list of conditions and the 
 * following disclaimer.
 *
 * Redistributions in binary form must reproduce the
 * above copyright notice, this list of conditions and 
 * the following disclaimer in the documentation 
 * and/or other materials provided with the distribution.
 *      
 * Neither the name of ARM nor the names of its
 * contributors may be used to endorse or promote products
 * derived from this software without specific prior written
 * permission.                        
 */ 

#include "int_master.h"
#include "gic_registers.h"
#include "virt_helpers.h"
#include "misc.h"
#include "events.h"
#include "vgiclib.h"

/*
 * The Big-little spftware needs to bother itself with
 * bareminimal vGIC configuration. 
 *
 * 1. Distributor. Security bits should be taken care of 
 * by the boot firmaware after a cold reset. Big-little
 * code should initialise private interrupts as secure
 * after a warm reset.
 *
 * 2. Physical Cpu interface. Initialised by us after
 * both warm and cold reset.
 *
 * 3. Virtual CPU interface (HYP view). Initialised by us 
 * after cold reset & restored after warm reset.
 *
 * 4. Virtual CPU interface (CPU view). Initialised by 
 * the payload software after cold reset and restored by 
 * us after a warm reset.
 */
static void gic_cpuinit()
{
        /* Disable the PCPUIF before configuring it. */
        write32(GIC_IC_PHY_BASE + GICC_CTL, 0x0);
        write32(GIC_IC_PHY_BASE + GICC_BP, 0x0);
        write32(GIC_IC_PHY_BASE + GICC_PRIMASK, 0xFF);
        /* Enable split EOI & Non-secure PCPUIF */
        write32(GIC_IC_PHY_BASE + GICC_CTL, 0x201);
}

void SetupVGIC(unsigned warm_reset)
{
        /* 
         * Initialise the HYP view Virtual CPU interface after
         * a cold reset
         */
        if (!warm_reset)
                vgic_init();

        /* Initialise the Physical cpu interface */
        gic_cpuinit();

        /*
         * Enable Virtual exceptions
         */
        write_hcr(read_hcr() | HCR_AMO | HCR_IMO | HCR_FMO);

        /*
         * TODO: Barriers not needed here as there will surely
         * be others further down the line before virtual 
         * exceptions are used.
         */
        return;
}