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-rw-r--r--bootwrapper/bootwrapper.h20
-rw-r--r--bootwrapper/c_start.c336
-rw-r--r--bootwrapper/helpers.h20
-rw-r--r--bootwrapper/uart.c56
-rw-r--r--bootwrapper/vgic.h8
5 files changed, 220 insertions, 220 deletions
diff --git a/bootwrapper/bootwrapper.h b/bootwrapper/bootwrapper.h
index f4e9987..739e8dd 100644
--- a/bootwrapper/bootwrapper.h
+++ b/bootwrapper/bootwrapper.h
@@ -18,7 +18,7 @@
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
- */
+ */
#ifndef __BOOTWRAPPER_H__
#define __BOOTWRAPPER_H__
@@ -48,14 +48,14 @@
#define FLAGS_SET 0x30
#define FLAGS_CLR 0x34
-#define VE_KFSCB_BASE 0x10020000 /* Kingfisher System Configuration Block */
-#define KFS_ID_OFFSET 0xFFC /* Kingfisher System Platform ID register offset (KFS_ID) */
-#define KFS_ID_ARCH_MASK 0x000F0000 /* Mask for extracting KFS architecture */
-#define KFS_ID_ARCH_SHIFT 16 /* Shift for extracting KFS architecture */
-#define KFS_CFG_R 0x30 /* Kingfisher System static configuration read register */
-#define ACTIVE_CLUSTER_MASK 0x3 /* Returns the value that was driven on the CFG_ACTIVECLUSTER configuration inputs at the last system power-on reset. */
-#define KFS_CFG_R_OFFSET 0x30 /* Kingfisher System Static Configuration Read register */
-#define ACTIVE_CLUSTER_MASK 0x3 /* Returns the value that was driven on the CFG_ACTIVECLUSTER configuration input */
+#define VE_KFSCB_BASE 0x10020000 /* Kingfisher System Configuration Block */
+#define KFS_ID_OFFSET 0xFFC /* Kingfisher System Platform ID register offset (KFS_ID) */
+#define KFS_ID_ARCH_MASK 0x000F0000 /* Mask for extracting KFS architecture */
+#define KFS_ID_ARCH_SHIFT 16 /* Shift for extracting KFS architecture */
+#define KFS_CFG_R 0x30 /* Kingfisher System static configuration read register */
+#define ACTIVE_CLUSTER_MASK 0x3 /* Returns the value that was driven on the CFG_ACTIVECLUSTER configuration inputs at the last system power-on reset. */
+#define KFS_CFG_R_OFFSET 0x30 /* Kingfisher System Static Configuration Read register */
+#define ACTIVE_CLUSTER_MASK 0x3 /* Returns the value that was driven on the CFG_ACTIVECLUSTER configuration input */
#define CLUSTER_CPU_COUNT(x) (((read32(VE_KFSCB_BASE + KFS_CFG_R) >> 16) >> (x << 2)) & 0xf)
#define write32(addr, val) (*(volatile unsigned int *)(addr) = (val))
@@ -65,4 +65,4 @@ extern void config_uart(void);
extern void drain_uart_fifo(void);
extern void start(void);
-#endif /* __BOOTWRAPPER_H__ */
+#endif /* __BOOTWRAPPER_H__ */
diff --git a/bootwrapper/c_start.c b/bootwrapper/c_start.c
index 148c0a3..977f59c 100644
--- a/bootwrapper/c_start.c
+++ b/bootwrapper/c_start.c
@@ -18,7 +18,7 @@
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
- */
+ */
#include <stdio.h>
#include <string.h>
@@ -40,12 +40,12 @@ volatile unsigned model_pen = 0;
unsigned gic_int_num(void)
{
- unsigned intcount = 0;
+ unsigned intcount = 0;
- intcount = read32(GIC_ID_PHY_BASE + GICD_CTR);
- intcount = ((intcount & 0x1F) + 1) * 32;
+ intcount = read32(GIC_ID_PHY_BASE + GICD_CTR);
+ intcount = ((intcount & 0x1F) + 1) * 32;
- return intcount;
+ return intcount;
}
/*
@@ -53,17 +53,17 @@ unsigned gic_int_num(void)
*/
void setup_gic_nonsecure(unsigned cluster_id, unsigned cpu_id)
{
- unsigned ctr = 0, num_ints = gic_int_num();
+ unsigned ctr = 0, num_ints = gic_int_num();
- /* Ensure all GIC interrupts are Non-Secure */
- write32(GIC_ID_PHY_BASE + GICD_SEC + (ctr << 2), 0xffffffff); /* IRQs 0-31 are Non-Secure */
- if (cpu_id == 0 && cluster_id == 0) {
- for (ctr = 1; ctr <= (num_ints >> 5); ctr++)
- write32(GIC_ID_PHY_BASE + GICD_SEC + (ctr << 2), 0xffffffff); /* Set all SPIs as non-secure */
- }
+ /* Ensure all GIC interrupts are Non-Secure */
+ write32(GIC_ID_PHY_BASE + GICD_SEC + (ctr << 2), 0xffffffff); /* IRQs 0-31 are Non-Secure */
+ if (cpu_id == 0 && cluster_id == 0) {
+ for (ctr = 1; ctr <= (num_ints >> 5); ctr++)
+ write32(GIC_ID_PHY_BASE + GICD_SEC + (ctr << 2), 0xffffffff); /* Set all SPIs as non-secure */
+ }
- /* Ensure all interrupts can get through the priority mask */
- write32(GIC_IC_PHY_BASE + GICC_PRIMASK, 0xff);
+ /* Ensure all interrupts can get through the priority mask */
+ write32(GIC_IC_PHY_BASE + GICC_PRIMASK, 0xff);
}
/*
@@ -71,13 +71,13 @@ void setup_gic_nonsecure(unsigned cluster_id, unsigned cpu_id)
*/
void kick(unsigned cpu_id, int secondary_cpus)
{
- int cpu_mask = ((1 << (secondary_cpus + 1)) - 1) & ~(1 << cpu_id);
+ int cpu_mask = ((1 << (secondary_cpus + 1)) - 1) & ~(1 << cpu_id);
- write32(VE_SYS_BASE + FLAGS_CLR, 0xffffffff); // clear the flags register
- write32(VE_SYS_BASE + FLAGS_SET, (unsigned)start); // set the start address in the flags register
- write32(GIC_ID_PHY_BASE, 0x1); // turn on the GIC distributor
- write32(GIC_IC_PHY_BASE, 0x1); // turn on the GIC CPU interface
- write32(GIC_ID_PHY_BASE + GICD_SW, cpu_mask << 16); // send an interrupt to everyone else
+ write32(VE_SYS_BASE + FLAGS_CLR, 0xffffffff); // clear the flags register
+ write32(VE_SYS_BASE + FLAGS_SET, (unsigned)start); // set the start address in the flags register
+ write32(GIC_ID_PHY_BASE, 0x1); // turn on the GIC distributor
+ write32(GIC_IC_PHY_BASE, 0x1); // turn on the GIC CPU interface
+ write32(GIC_ID_PHY_BASE + GICD_SW, cpu_mask << 16); // send an interrupt to everyone else
}
/*
@@ -86,55 +86,54 @@ void kick(unsigned cpu_id, int secondary_cpus)
*/
void secondary_main(unsigned cluster_id, unsigned cpu_id)
{
- unsigned val;
- void (*secondary_start) (void);
-
- /* Ensure I cache is on and interrupts are masked */
- inv_icache_all();
- write_sctlr(read_sctlr() | (1 << 12));
- write_cpsr(read_cpsr() | 0x80);
-
- /* tell CPU0 that we are ready */
- cpus_ready[cluster_id][cpu_id] = 1;
-
- /*
- * We're not the primary core, so we need to wait for the primary
- * core to tell us what to do. While doing that, go into WFI so we
- * don't just sit here consuming system resources (i.e. bus
- * badwidth); make sure a soft IRQ gets through to the core, but
- * don't actually take the interrupt - that way we'll come out of
- * WFI without worrying about interrupt vectors (which may have gone
- * away, since the primary core is playing with our memory).
- */
- write32(GIC_IC_PHY_BASE + GICC_CTL, 0x1); /* Enable GIC CPU Interface */
- write32(GIC_IC_PHY_BASE + GICC_PRIMASK, 0x000000f0); /* Set Priority Mask to allow interrupts */
-
- /* If the start address isn't already set, go to sleep */
- while (val = read32(VE_SYS_BASE + FLAGS_SET), val == 0
- || val == (unsigned)start) {
- wfi();
- /* Acknowledge the interrupt that woke us */
- /* Read the Acknowledge register, write End Of Interrupt */
- write32(GIC_IC_PHY_BASE + GICC_EOI,
- read32(GIC_IC_PHY_BASE + GICC_INTACK));
- }
-
- /* TODO: If MMU is enabled, then synchronise caches here */
- secondary_start = (void (*)())val;
- secondary_start(); /* No return from here */
+ unsigned val;
+ void (*secondary_start) (void);
+
+ /* Ensure I cache is on and interrupts are masked */
+ inv_icache_all();
+ write_sctlr(read_sctlr() | (1 << 12));
+ write_cpsr(read_cpsr() | 0x80);
+
+ /* tell CPU0 that we are ready */
+ cpus_ready[cluster_id][cpu_id] = 1;
+
+ /*
+ * We're not the primary core, so we need to wait for the primary
+ * core to tell us what to do. While doing that, go into WFI so we
+ * don't just sit here consuming system resources (i.e. bus
+ * badwidth); make sure a soft IRQ gets through to the core, but
+ * don't actually take the interrupt - that way we'll come out of
+ * WFI without worrying about interrupt vectors (which may have gone
+ * away, since the primary core is playing with our memory).
+ */
+ write32(GIC_IC_PHY_BASE + GICC_CTL, 0x1); /* Enable GIC CPU Interface */
+ write32(GIC_IC_PHY_BASE + GICC_PRIMASK, 0x000000f0); /* Set Priority Mask to allow interrupts */
+
+ /* If the start address isn't already set, go to sleep */
+ while (val = read32(VE_SYS_BASE + FLAGS_SET), val == 0
+ || val == (unsigned)start) {
+ wfi();
+ /* Acknowledge the interrupt that woke us */
+ /* Read the Acknowledge register, write End Of Interrupt */
+ write32(GIC_IC_PHY_BASE + GICC_EOI,
+ read32(GIC_IC_PHY_BASE + GICC_INTACK));
+ }
+
+ /* TODO: If MMU is enabled, then synchronise caches here */
+ secondary_start = (void (*)())val;
+ secondary_start(); /* No return from here */
}
void wait_for_secondaries(unsigned active_clusters, unsigned secondary_cpus)
{
- int i, j, ready;
+ int i, j, ready;
- printf("Waiting for %d secondary CPUs\n", secondary_cpus);
+ printf("Waiting for %d secondary CPUs\n", secondary_cpus);
- while (TRUE) {
- ready = 0;
+ while (TRUE) {
+ ready = 0;
- for (i = 0; i < active_clusters; i++)
- {
+ for (i = 0; i < active_clusters; i++) {
for (j = 0; j < NUM_CPUS; j++) {
if (cpus_ready[i][j]) {
++ready;
@@ -142,15 +141,15 @@ void wait_for_secondaries(unsigned active_clusters, unsigned secondary_cpus)
}
}
- if (ready == secondary_cpus) {
- break;
- }
+ if (ready == secondary_cpus) {
+ break;
+ }
- /* Don't thrash the memory system, give the secondaries some time */
- for (j = 0; j < 1000; ++j) {
- __nop();
- }
- }
+ /* Don't thrash the memory system, give the secondaries some time */
+ for (j = 0; j < 1000; ++j) {
+ __nop();
+ }
+ }
}
/*
@@ -161,29 +160,30 @@ void wait_for_secondaries(unsigned active_clusters, unsigned secondary_cpus)
*/
int get_cluster_count(void)
{
- unsigned int kfs_id, active_clusters;
- int num_clusters = 0;
-
- kfs_id = read32(VE_KFSCB_BASE + KFS_ID_OFFSET);
-
- switch (((kfs_id & KFS_ID_ARCH_MASK) >> KFS_ID_ARCH_SHIFT))
- {
- case 0:
- case 1:
- case 2:
- case 3:
- active_clusters = read32(VE_KFSCB_BASE + KFS_CFG_R_OFFSET) & ACTIVE_CLUSTER_MASK;
- num_clusters = (active_clusters == 0x3) ? 2 : 1;
- break;
- }
-
- return num_clusters;
+ unsigned int kfs_id, active_clusters;
+ int num_clusters = 0;
+
+ kfs_id = read32(VE_KFSCB_BASE + KFS_ID_OFFSET);
+
+ switch (((kfs_id & KFS_ID_ARCH_MASK) >> KFS_ID_ARCH_SHIFT)) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ active_clusters =
+ read32(VE_KFSCB_BASE +
+ KFS_CFG_R_OFFSET) & ACTIVE_CLUSTER_MASK;
+ num_clusters = (active_clusters == 0x3) ? 2 : 1;
+ break;
+ }
+
+ return num_clusters;
}
void c_start(void)
{
- unsigned cpu_id = read_cpuid();
- unsigned cluster_id = read_clusterid();
+ unsigned cpu_id = read_cpuid();
+ unsigned cluster_id = read_clusterid();
unsigned secondary_cpus = 0;
unsigned platform = VERSATILE_EXPRESS;
unsigned active_clusters = get_cluster_count();
@@ -193,83 +193,83 @@ void c_start(void)
secondary_cpus += CLUSTER_CPU_COUNT(!cluster_id);
}
- write_vbar((unsigned)&vector_table);
- write_mvbar((unsigned)&bl_sec_image);
- if (cpu_id == 0 && cluster_id == 0)
- config_uart();
-
- enable_user_perfmon_access();
- enable_perfmon();
- enable_swp();
- write_cpacr(read_cpacr() | 0xfffffff);
- write_nsacr(0x00073fff);
- enable_coherency();
-
- /* Also grant NS access to CCI registers */
- if (cpu_id == 0 && cluster_id == 0)
- write32(CCI_BASE + SECURE_ACCESS_REG, 0x1);
-
- /*
- * Secondaries wait here while initialisation of global peripherals is done
- */
- if (model_pen == 0 && (cpu_id || cluster_id)) {
- do {
- wfe();
- } while (model_pen == 0);
- }
-
- setup_gic_nonsecure(cluster_id, cpu_id);
-
- if (cpu_id == 0 && cluster_id == 0) {
- model_pen = 1;
- dsb();
- sev();
- }
-
- enter_monitor_mode();
- write_scr(0x131); /* HVC, NS, FW and AW bits */
- write_cnthctl(PL1PCTEN | PL1PCEN);
- write_cntkctl(PL0PCTEN | PL0VCTEN | PL0VTEN | PL0PTEN);
- write_cntfrq(CP15_TIMER_FREQ);
-
- /* Start secondary CPUs, if any */
- if (cpu_id == 0 && cluster_id == 0 && secondary_cpus > 0) {
- printf("Kicking %d secondary CPU(s)\n", secondary_cpus);
- drain_uart_fifo();
- kick(cpu_id, secondary_cpus);
- }
-
- enter_nonsecure_world((unsigned)bl_image);
-
- /* Secondary CPUs go off to secondary_main() */
- if (cpu_id || cluster_id) {
- secondary_main(cluster_id, cpu_id); /* no return */
- }
-
- /* Primary waits for the secondaries to get ready before loading the payload */
- wait_for_secondaries(active_clusters, secondary_cpus);
-
- /* Load the payload kernel */
- printf("Kernel at 0x%x\n", kernel_start);
-
- if (thumb)
- kernel_start_address =
- (void (*)(int, int, int, int))((unsigned)kernel_start | 1);
- else
- kernel_start_address = kernel_start;
-
- printf("Kernel entry point 0x%x (%s)\n", kernel_start_address,
- ((unsigned)kernel_start_address & 1) ? "thumb" : "arm");
-
- drain_uart_fifo();
-
- /* Clear FLAGS register, as this is what Linux expects to find */
- write32(VE_SYS_BASE + FLAGS_CLR, 0xffffffff);
-
- /* TODO: If MMU is enabled then caches need to be cleaned here */
-
- /* Start the kernel */
- kernel_start_address(0, platform & PLATFORM_MASK, 0, 0); /* No return from here */
-
- return;
+ write_vbar((unsigned)&vector_table);
+ write_mvbar((unsigned)&bl_sec_image);
+ if (cpu_id == 0 && cluster_id == 0)
+ config_uart();
+
+ enable_user_perfmon_access();
+ enable_perfmon();
+ enable_swp();
+ write_cpacr(read_cpacr() | 0xfffffff);
+ write_nsacr(0x00073fff);
+ enable_coherency();
+
+ /* Also grant NS access to CCI registers */
+ if (cpu_id == 0 && cluster_id == 0)
+ write32(CCI_BASE + SECURE_ACCESS_REG, 0x1);
+
+ /*
+ * Secondaries wait here while initialisation of global peripherals is done
+ */
+ if (model_pen == 0 && (cpu_id || cluster_id)) {
+ do {
+ wfe();
+ } while (model_pen == 0);
+ }
+
+ setup_gic_nonsecure(cluster_id, cpu_id);
+
+ if (cpu_id == 0 && cluster_id == 0) {
+ model_pen = 1;
+ dsb();
+ sev();
+ }
+
+ enter_monitor_mode();
+ write_scr(0x131); /* HVC, NS, FW and AW bits */
+ write_cnthctl(PL1PCTEN | PL1PCEN);
+ write_cntkctl(PL0PCTEN | PL0VCTEN | PL0VTEN | PL0PTEN);
+ write_cntfrq(CP15_TIMER_FREQ);
+
+ /* Start secondary CPUs, if any */
+ if (cpu_id == 0 && cluster_id == 0 && secondary_cpus > 0) {
+ printf("Kicking %d secondary CPU(s)\n", secondary_cpus);
+ drain_uart_fifo();
+ kick(cpu_id, secondary_cpus);
+ }
+
+ enter_nonsecure_world((unsigned)bl_image);
+
+ /* Secondary CPUs go off to secondary_main() */
+ if (cpu_id || cluster_id) {
+ secondary_main(cluster_id, cpu_id); /* no return */
+ }
+
+ /* Primary waits for the secondaries to get ready before loading the payload */
+ wait_for_secondaries(active_clusters, secondary_cpus);
+
+ /* Load the payload kernel */
+ printf("Kernel at 0x%x\n", kernel_start);
+
+ if (thumb)
+ kernel_start_address =
+ (void (*)(int, int, int, int))((unsigned)kernel_start | 1);
+ else
+ kernel_start_address = kernel_start;
+
+ printf("Kernel entry point 0x%x (%s)\n", kernel_start_address,
+ ((unsigned)kernel_start_address & 1) ? "thumb" : "arm");
+
+ drain_uart_fifo();
+
+ /* Clear FLAGS register, as this is what Linux expects to find */
+ write32(VE_SYS_BASE + FLAGS_CLR, 0xffffffff);
+
+ /* TODO: If MMU is enabled then caches need to be cleaned here */
+
+ /* Start the kernel */
+ kernel_start_address(0, platform & PLATFORM_MASK, 0, 0); /* No return from here */
+
+ return;
}
diff --git a/bootwrapper/helpers.h b/bootwrapper/helpers.h
index 862e1da..07ffc47 100644
--- a/bootwrapper/helpers.h
+++ b/bootwrapper/helpers.h
@@ -18,7 +18,7 @@
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
- */
+ */
#ifndef _VIRT_HELPERS_H_
#define _VIRT_HELPERS_H_
@@ -157,7 +157,7 @@ extern unsigned read_cntp_ctl(void);
extern unsigned read_cntp_tval(void);
extern unsigned num_secondaries(void);
extern unsigned *copy_words(volatile unsigned *destination,
- volatile unsigned *source, unsigned num_words);
+ volatile unsigned *source, unsigned num_words);
extern unsigned *get_sp(unsigned, unsigned);
/*
@@ -199,22 +199,22 @@ extern void enter_nonsecure_world(unsigned);
* GIC functions
*/
extern void save_gic_interface(unsigned int *pointer,
- unsigned gic_interface_address);
+ unsigned gic_interface_address);
extern int save_gic_distributor_private(unsigned int *pointer,
- unsigned gic_distributor_address);
+ unsigned gic_distributor_address);
extern int save_gic_distributor_shared(unsigned int *pointer,
- unsigned gic_distributor_address);
+ unsigned gic_distributor_address);
extern void restore_gic_interface(unsigned int *pointer,
- unsigned gic_interface_address);
+ unsigned gic_interface_address);
extern void restore_gic_distributor_private(unsigned int *pointer,
- unsigned gic_distributor_address);
+ unsigned gic_distributor_address);
extern void restore_gic_distributor_shared(unsigned int *pointer,
- unsigned gic_distributor_address);
+ unsigned gic_distributor_address);
extern void disable_gic_dist(unsigned int *tmp,
- volatile unsigned int *dist_base);
+ volatile unsigned int *dist_base);
extern void enable_gic_dist(unsigned int tmp, volatile unsigned int *dist_base);
extern void switcher_exit(void);
extern void hyp_save(unsigned, unsigned);
-#endif /* _VIRT_HELPERS_H_ */
+#endif /* _VIRT_HELPERS_H_ */
diff --git a/bootwrapper/uart.c b/bootwrapper/uart.c
index 5c858f6..8ea104f 100644
--- a/bootwrapper/uart.c
+++ b/bootwrapper/uart.c
@@ -18,7 +18,7 @@
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
- */
+ */
/*
* uart.c - boot code to output characters on a PL011 uart
@@ -56,61 +56,61 @@ static unsigned uart_base = NULL;
void config_uart(void)
{
- uart_base = UART0_BASE;
- write32(uart_base + PL011_CR, 0);
- write32(uart_base + PL011_FBRD, 0x01);
- write32(uart_base + PL011_IBRD, 0x27);
- write32(uart_base + PL011_LCRH, 0x70);
- write32(uart_base + PL011_CR, 0xf01); /* TXE|RXE|En|DTR|CTS */
+ uart_base = UART0_BASE;
+ write32(uart_base + PL011_CR, 0);
+ write32(uart_base + PL011_FBRD, 0x01);
+ write32(uart_base + PL011_IBRD, 0x27);
+ write32(uart_base + PL011_LCRH, 0x70);
+ write32(uart_base + PL011_CR, 0xf01); /* TXE|RXE|En|DTR|CTS */
}
void drain_uart_fifo(void)
{
- while (!(read32(uart_base + PL011_FR) & PL011_TXFE)) {
- /* Do nothing */
- }
+ while (!(read32(uart_base + PL011_FR) & PL011_TXFE)) {
+ /* Do nothing */
+ }
}
static __inline void wait_for_space(void)
{
- while ((read32(uart_base + PL011_FR) & PL011_TXFF)) {
- /* Do nothing */
- }
+ while ((read32(uart_base + PL011_FR) & PL011_TXFF)) {
+ /* Do nothing */
+ }
}
void output_char(int c)
{
- if (c == '\n') {
- wait_for_space();
- write32(uart_base + PL011_DR, '\r');
- }
- wait_for_space();
- write32(uart_base + PL011_DR, c);
+ if (c == '\n') {
+ wait_for_space();
+ write32(uart_base + PL011_DR, '\r');
+ }
+ wait_for_space();
+ write32(uart_base + PL011_DR, c);
}
void output_string(const char *string)
{
- int i;
+ int i;
- for (i = 0; string[i]; ++i) {
- output_char(string[i]);
- }
+ for (i = 0; string[i]; ++i) {
+ output_char(string[i]);
+ }
}
void hexword(unsigned value)
{
- printf(" 0x%8.8x", value);
- drain_uart_fifo();
+ printf(" 0x%8.8x", value);
+ drain_uart_fifo();
}
typedef struct __FILE {
- int dummy;
+ int dummy;
} FILE;
FILE __stdout;
int fputc(int c, FILE * f)
{
- output_char(c);
- return c;
+ output_char(c);
+ return c;
}
diff --git a/bootwrapper/vgic.h b/bootwrapper/vgic.h
index 1c79a6a..084e593 100644
--- a/bootwrapper/vgic.h
+++ b/bootwrapper/vgic.h
@@ -18,13 +18,13 @@
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
- */
+ */
#ifndef __VGIC_H__
#define __VGIC_H__
-#define GIC_ID_PHY_BASE 0x2C001000 /* Physical Distributor */
-#define GIC_IC_PHY_BASE 0x2C002000 /* Physical CPU interface */
+#define GIC_ID_PHY_BASE 0x2C001000 /* Physical Distributor */
+#define GIC_IC_PHY_BASE 0x2C002000 /* Physical CPU interface */
/* Distributor interface registers */
#define GICD_CTL 0x0
@@ -54,4 +54,4 @@
#define GICC_DEACTIVATE 0x1000
#define GICC_PRIODROP GICC_EOI
-#endif /* __VGIC_H__ */
+#endif /* __VGIC_H__ */